DDR Termination Regulator
TJ2996
source and sink a higher maximum continuous current. PVIN can be also connected to a 1.8V rail and it
has a limitation of maximum continuous current. PVIN should be connected to a voltage higher than a
1.5V rail.
FIGURE 9. HSTL Application
QDR APPLICATIONS
Quad data rate (QDR) applications utilize multiple channels for improved memory performance.
However, this increase in bus lines has the effect of increasing the current levels required for termination.
The recommended approach in terminating multiple channels is to use a dedicated TJ2996 for each
channel. This simplifies layout and reduces the internal power dissipation for each regulator. Separate
VREF signals can be used for each DIMM bank from the corresponding regulator with the chipset
reference provided by a local resistor divider or one of the TJ2996 signals. Because VREF and VTT are
expected to track and the part to part variations are minor, there should be little difference between the
reference signals of each TJ2996.
FIGURE 10. Typical SSTL-2 Application Circuit
OUTPUT CAPACITOR SELECTION
For applications utilizing the TJ2996 to terminate SSTL-2 I/O signals the typical application circuit
shown in Figure 8 can be implemented. This circuit permits termination in a minimum amount of board
space and component count. Capacitor selection can be varied depending on the number of lines
terminated and the maximum load transient. However, with motherboards and other applications where
VTT is distributed across a long plane it is advisable to use multiple bulk capacitors and addition to high
frequency decoupling. Figure 9 shown below depicts an example circuit where 2 bulk output capacitors
could be situated at both ends of the VTT plane for optimal placement. Large aluminum electrolytic
capacitors are used for their low ESR and low cost.
Jul. 2010 - Rev. 1.5.3
13/14
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
