DDR Termination Regulator
TJ2996
TYPICAL APPLICATION INFORMATION
Several different application circuits have been shown in Figure 2 through Figure 11 to illustrate some
of the options that are possible in configuring the TJ2996.
SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL-2 termination scheme it is recommended to
connect all the input rails to the 2.5V rail. This provides an optimal trade-off between power dissipation
and component count and selection. An example of this circuit can be seen in Figure 2.
FIGURE 2. Recommended SSTL-2 Implementation
If power dissipation or efficiency is a major concern then the TJ2996 has the ability to operate on split
power rails. The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog
circuitry (AVIN) can be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal
power dissipation to be lowered when sourcing current from VTT. The disadvantage of this circuit is that
the maximum continuous current is reduced because of the lower rail voltage, although it is adequate for
all motherboard SSTL-2 applications. Increasing the output capacitance can also help if periods of large
load transients will be encountered.
FIGURE 3. Lower Power Dissipation SSTL-2 Implementation
The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not
desirable to use 2.5V is to connect the TJ2996 power rail to 3.3V. In this situation AVIN will be limited to
operation on the 3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to
provide the maximum continuous output current at the downside of higher thermal dissipation. Care
should be taken to prevent the TJ2996 from experiencing large current levels which cause the junction
temperature to exceed the maximum. Because of this risk it is not recommended to supply the output
stage with a voltage higher than a nominal 3.3V rail.
Jul. 2010 - Rev. 1.5.3
10/14
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
