DDR Termination Regulator
TJ2996
LEVEL SHIFTING
If standards other than SSTL-2 are required, such as SSTL-3, it may be necessary to use a different
scaling factor than 0.5 times VDDQ for regulating the output voltage. Several options are available to
scale the output to any voltage required. One method is to level shift the output by using feedback
resistors from VTT to the VSENSE pin. This has been illustrated in Figures 7 and 8. Figure 7 shows how
to use two resistors to level shift VTT above the internal reference voltage of VDDQ / 2. To calculate the
exact voltage at VTT the following equation can be used
VTT = VDDQ / 2 ( 1 + R1 / R2 )
FIGURE 7. Increasing VTT by Level Shifting
Conversely, the R2 resistor can be placed between VSENSE and VDDQ to shift the VTT output lower than
the internal reference voltage of VDDQ / 2. The equations relating VTT and the resistors can be seen
below:
VTT = VDDQ / 2 (1 - R1 / R2)
FIGURE 8. Decreasing VTT by Level Shifting
HSTL APPLICATIONS
The TJ2996 can be easily adapted for HSTL applications by connecting VDDQ to the 1.5V rail. This will
produce a VTT and VREF voltage of approximately 0.75V for the termination resistors. It is possible to
connect PVIN to higher than a 2.5V rail. Care should be taken to do not exceed the maximum junction
temperature as the thermal dissipation increases with lower VTT output voltages (For more information,
refer to the Thermal Dissipation section.). The advantage of this configuration is that it has the ability to
Jul. 2010 - Rev. 1.5.3
12/14
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
