The value of resistors R1 and R2
are calculated with the following
formulas
R1 and R2 provide a constant
voltage source at the base of a
PNP transistor at Q2. The con-
stant voltage at the base of Q2 is
raised by 0.7 volts at the emitter.
The constant emitter voltage plus
the regulated VDD supply are
present across resistor R3.
value of resistor R3 which deter-
mines the drain current Ids. In the
example R3=23.3Ω. Equation (3)
calculates the voltage required at
the junction of resistors R1 and R2.
This voltage plus the step-up of the
base emitter junction determines
the regulated Vds. Equations (4)
and (5) are solved simultaneously
to determine the value of resistors
R1 and R2. In the example
Vgs
R1 =
(2)
p
IBB
(Vds – Vgs) R1
Vgs
R2 =
(3)
Constant voltage across R3
p
provides a constant current
supply for the drain current.
Resistors R1 and R2 are used to
set the desired Vds. The combined
Example Circuit
R1=1450Ω and R2 =1050Ω. Resis-
tor R7 is chosen to be 1 kΩ. This
VDD = 5V
Vds = 3V
Ids = 60 mA
Vgs = 0.58V
series value of these resistors also resistor keeps a small amount of
sets the amount of extra current
consumed by the bias network.
The equations that describe the
circuit’s operation are as follows.
current flowing through Q2 to help
maintain bias stability. R6 is
chosen to be 10 KΩ. This value of
resistance is high enough to limit
Q1 gate current in the presence of
high RF drive levels as experienced
when Q1 is driven to the P1dB gain
compression point. C7 provides a
low frequency bypass to keep noise
from Q2 effecting the operation of
Q1. C7 is typically 0.1 µF.
Choose IBB to be at least 10X the
maximum expected gate leakage
current. IBB was chosen to be
2 mA for this example. Using
equations (1), (2), and (3) the
resistors are calculated as follows
VE = Vds + (Ids • R4)
(1)
VDD – VE
R3 =
(2)
(3)
p
Ids
R1 = 290Ω
R2 = 1210Ω
R3 = 32.3Ω
VB = VE – VBE
R1
VB =
Maximum Suggested Gate Current
The maximum suggested gate
current for the ATF-541M4 is
2 mA. Incorporating resistor R5
in the passive bias network or
resistor R6 in the active bias
network safely limits gate current
to 500 µA at P1dB drive levels.
In order to minimize component
count in the passive biased
amplifier circuit, the 3 resistor
bias circuit consisting of R1, R2,
and R5 can be simplified if
desired. R5 can be removed if R1
is replaced with a 4.7KΩ resistor
and if R2 is replaced with a 27KΩ
resistor. This combination should
limit gate current to a safe level.
Active Bias
VDD
(4)
(5)
p
R1 + R2
Active biasing provides a means
of keeping the quiescent bias
point constant over temperature
and constant over lot to lot
variations in device dc perfor-
mance. The advantage of the
active biasing of an enhancement
mode PHEMT versus a depletion
mode PHEMT is that a negative
power source is not required. The
techniques of active biasing an
enhancement mode device are
very similar to those used to bias
a bipolar junction transistor.
VDD = IBB (R1 + R2)
Rearranging equation (4)
provides the following formula
R1 (VDD – VB)
R2 =
(4A)
p
VB
and rearranging equation (5)
provides the follow formula
VDD
9
R1 =
(5A)
VDD – VB
p
IBB 1 +
(
)
VB
An active bias scheme is shown
in Figure 2.
C4
OUTPUT
Example Circuit
C1
INPUT
Q1
Zo
Zo
PCB Layout
VDD = 5V
Vds = 3V
Ids = 60 mA
R4 = 10Ω
VBE = 0.7V
L1
L4
A suggested PCB pad print for
the miniature, Minipak 1412
package used by the ATF-541M4
is shown in Figure 3.
L2
L3
C2
C3
C5
R4
R5
R6
C7
Q2
C6
Equation (1) calculates the re-
Vdd
quired voltage at the emitter of the
PNP transistor based on desired
Vds and Ids through resistor R4 to
be 3.6V. Equation (2) calculates the
R7
R3
R2
R1
Figure 2. Typical ATF-541M4 LNA with Active
Biasing.
13
HP [ HEWLETT-PACKARD ]
