Capacitors C2 and C5 provide a
low impedance in-band RF
Whereas a depletion mode
ATF-541M4 Applications
Information
PHEMT pulls maximum drain
current when Vgs=0V, an en-
hancement mode PHEMT pulls
only a small amount of leakage
current when Vgs=0V. Only when
Vgs is increased above Vto, the
bypass for the matching net-
works. Resistors R3 and R4
provide a very important low
frequency termination for the
device. The resistive termination
Introduction
Agilent Technologies’s
ATF-541M4 is a low noise
enhancement mode PHEMT
designed for use in low cost
commercial applications in the
VHF through 6 GHz frequency
range. As opposed to a typical
depletion mode PHEMT where the
gate must be made negative with
respect to the source for proper
operation, an enhancement mode
PHEMT requires that the gate be
made more positive than the
source for normal operation.
Therefore a negative power
supply voltage is not required for
an enhancement mode device.
Biasing an enhancement mode
PHEMT is much like biasing the
typical bipolar junction transistor.
Instead of a 0.7V base to emitter
voltage, the ATF-541M4 enhance-
ment mode PHEMT requires a
nominal 0.58V potential between
the gate and source for a nominal
drain current of 60 mA.
improves low frequency stability. device threshold voltage, will
Capacitors C3 and C6 provide
the RF bypass for resistors R3
and R4. Their value should be
chosen carefully as C3 and C6
also provide a termination for
low frequency mixing products.
These mixing products are as a
result of two or more in-band
signals mixing and producing
third order in-band distortion
products. The low frequency or
difference mixing products are
terminated by C3 and C6. For
best suppression of third order
distortion products based on the
CDMA 1.25 MHz signal spacing,
C3 and C6 should be 0.1 uF in
value. Smaller values of capaci-
tance will not suppress the
generation of the 1.25 MHz
difference signal and as a result
will show up as poorer two tone
IP3 results.
drain current start to flow. At a
Vds of 3V and a nominal Vgs of
0.58V, the drain current Id will be
approximately 60 mA. The data
sheet suggests a minimum and
maximum Vgs over which the
desired amount of drain current
will be achieved. It is also impor-
tant to note that if the gate
terminal is left open circuited,
the device will pull some amount
of drain current due to leakage
current creating a voltage differ-
ential between the gate and
source terminals.
Passive Biasing
Passive biasing of the ATF-541M4
is accomplished by the use of a
voltage divider consisting of R1
and R2 connected to the gate of
the device. The voltage for the
divider is derived from the drain
voltage. This provides a form of
voltage feedback (through the use
of R3) to help keep drain current
constant. Resistor R5 (approxi-
mately 10KΩ) is added to limit
the gate current of enhancement
mode devices such as the
Matching Networks
C4
OUTPUT
C1
INPUT
Q1
L2
The techniques for impedance
matching an enhancement mode
device are very similar to those for
matching a depletion mode device.
The only difference is in the
Zo
Zo
L1
L4
L3
C2
C3
C5
R3
R4
R5
method of supplying gate bias. S
and Noise Parameters for various
bias conditions are listed in this
data sheet. The circuit shown in
Figure 1 shows a typical LNA
circuit normally used for 900 and
1900 MHz applications. (Consult
the Agilent Technologies web site
for application notes covering
specific designs and applications).
High pass impedance matching
networks consisting of L1/C1 and
L4/C4 provide the appropriate
match for noise figure, gain, S11
and S22. The high pass structure
also provides low frequency gain
reduction which can be beneficial
from the standpoint of improving
out-of-band rejection.
ATF-541M4. This is especially
important when the device is
driven to P1dB or Psat.
C6
R1
R2
Vdd
Resistor R3 is calculated based
on desired Vds, Ids and available
power supply voltage.
Figure 1. Typical ATF-541M4 LNA with Passive
Biasing.
Bias Networks
VDD – Vds
R3 =
(1)
One of the major advantages of
the enhancement mode technol-
ogy is that it allows the designer
to be able to dc ground the
source leads and then merely
apply a positive voltage on the
gate to set the desired amount of
quiescent drain current Id.
p
Ids + IBB
VDD is the power supply voltage.
Vds is the device drain to source
voltage.
Ids is the desired drain current.
IBB is the current flowing
through the R1/R2 resistor
voltage divider network.
12
HP [ HEWLETT-PACKARD ]
