RF42/43
Register 56h. Modem Test
Bit
D7
bcrfbyp
R/w
D6
slicfbyp
R/w
D5
dttype
R/w
D4
oscdeten
R/w
D3
ookth
R/w
D2
refclksel
R/w
D1
refclkinv
R/w
D0
distogg
R/w
Name
Type
Reset value = 00000000
Bit
7
Name
bcrfbyp
slicfbyp
Function
If set, BCR phase compensation will be bypassed.
If set, slicer phase compensation will be bypassed.
Dithering Type.
6
dttype
5
If low and dither enabled, we add +1/0, otherwise if high and dithering enabled,
we add ±1.
If low, the ADC Oscillation Detection mechanism is allowed to work. If set, we
disable the function.
oscdeten
ookth
4
3
If set, in OOK mode, the slicer threshold will be estimated by 8 bits of preamble.
By default, this bit is low and the demod estimate the threshold after 4 bits.
Delta-Sigma Reference Clock Source Selection
refclksel
2
1:
0:
10 MHz
PLL
refclkinv
distogg
1
0
Delta-Sigma Reference Clock Inversion Enable.
If reset, the discriminator toggling is disabled.
Register 57h. Charge Pump Test
Bit
D7
pfdrst
R/w
D6
fbdiv_rst
R/w
D5
cpforceup
R/w
D4
cpforcedn
R/w
D3
cdonly
R/w
D2
D1
cdcurr[2:0]
R/w
D0
Name
Type
Reset value = 00000000
Bit
7
Name
pfdrst
Function
Direct Control to Analog.
Direct Control to Analog.
Charge Pump Force Up.
Charge Pump Force Down.
Charge Pump DC Offset Only.
fbdiv_rst
cpforceup
cpforcedn
cdonly
6
5
4
3
cdcurr[2:0]
2:0
Charge Pump DC Current Selection.
88
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