RF42/43
The total settling time (cold start) of the PLL after the calibration can be calculated as TCS = TS + TO.
Register 53h. PLL Tune Time
Bit
D7
D6
D5
D4
D3
D2
D1
pllts0
R/w
D0
pllts[4:0]
R/w
Name
Type
Reset value = 01010010
Bit
Name
Function
PLL Soft Settling Time (TS).
This register will set the settling time for the PLL from a previous locked
7:3
pllts[4:0]
frequency in Tune mode. The value is configurable between 0 μs and 310 μs,
in 10 μs intervals. The default plltime corresponds to 100 μs. See formula
above.
PLL Settling Time (TO).
This register will set the time allowed for PLL settling after the calibrations are
completed. The value is configurable between 0 μs and 70 μs, in 10 μs steps.
The default pllt0 corresponds to 20 μs. See formula above.
2:0
pllts0t
Register 54h. PA Boost
Bit
D7
D6
D5
D4
inv_pre_th
R/w
D3
D2
D1
ldo_pa_boost
R/w
D0
pa_vbias_boost
R/w
Reserved[7:6]
R/w
Name
Type
Reset value = 01010100
Bit
7:6
5:2
1
Name
Function
Reserved[7:6]
inv_pre_th[5:2]
ldo_pa_boost
pa_vbias_boost
Reserved.
Invalid Preamble Threshold.
LDO PA Boost.
0
PA VBIAS Boost.
Invalid preamble will be evaluated during this period: (invalid_preamble_Threshold x 4) x Bit Rate period.
86
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