RF42/43
Register 04h. Interrupt/Status 2
Bit
D7
D6
D5
D4
D3
iwut
R
D2
ilbd
R
D1
ichiprdy
R
D0
Reserved
R
ipor
Name
Type
R
Reset value = xxxxxxxx
Bit
Name
Function
7：4
Reserved
Reserved.
Wake-Up-Timer.
3
2
iwut
ilbd
On the expiration of programmed wake-up timer this bit will be set to 1.
Low Battery Detect.
When a low battery event is been detected this bit will be set to 1. This interrupt
event is saved even if it is not enabled by the mask register bit and causes an
interrupt after it is enabled.
Chip Ready (XTAL).
1
0
ichiprdy
ipor
When a chip ready event has been detected this bit will be set to 1.
Power-on-Reset (POR).
When the chip detects a Power on Reset above the desired setting this bit will be
set to 1.
When any of the Interrupt/Status Register 2 bits change state from 0 to 1 the control block will notify the microcontroller
by setting the nIRQ pin LOW if it is enabled in the Interrupt Enable 2 register. The nIRQ pin will go to HIGH and all the
enabled interrupt bits will be cleared when the microcontroller reads this address. If any of these bits is not enabled in
the Interrupt Enable 2 register then it becomes a status signal that can be read anytime in the same location and will
not be cleared by reading the register.
59
Tel: +86-755-82973805
Fax: +86-755-82973550
E-mail: sales@hoperf.com
http://www.hoperf.com
HOPERF [ HOPERF ]
