RF42/43
Table 18. Interrupt or Status 1 Bit Set/Clear Description
Status
Name
ifferr
Set/Clear Conditions
Bit
7
Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset.
Set when the number of bytes written to TX FIFO is greater than the Almost Full
threshold. Automatically cleared at the start of transmission when the number of
bytes in the FIFO is less than or equal to the threshold.
Set when the number of bytes in the TX FIFO is less than or equal to the Almost
Empty threshold. Automatically cleared when the number of data bytes in the TX
FIFO is above the Almost Empty threshold.
6
5
itxffafull
itxffaem
4
3
Reserved
iext
Reserved.
External interrupt source.
Set once a packet is successfully sent (no TX abort). Cleared upon leaving FIFO
mode or at the start of a new transmission.
2
ipksent
1:0
Reserved
Reserved.
Table 19. When are Individual Status Bits Set/Cleared if not Enabled as Interrupts?
Status
Name
Set/Clear Conditions
Bit
Set if there is a FIFO Overflow or Underflow. It is cleared only by applying FIFO
reset to the specific FIFO that caused the condition.
7
ifferr
Will be set when the number of bytes written to TX FIFO is greater than the
Almost Full threshold set by SPI. It is automatically cleared when we start
transmitting and the FIFO data is read out and the number of bytes left in the
FIFO is smaller or equal to the threshold).
6
5
itxffafull
Will be set when the number of bytes (not yet transmitted) in TX FIFO is smaller
or equal than the Almost Empty threshold set by SPI. It is automatically cleared
when we write enough data to TX FIFO so that the number of data bytes not yet
transmitted is above the Almost Empty threshold.
itxffaem
4
3
Reserved
iext
Reserved.
External interrupt source.
Will go high once a packet is sent all the way through (no TX abort). This status
will be cleaned if 1) We leave FIFO mode or 2) In FIFO mode we start a new
transmission.
2
ipksent
1:0
Reserved
Reserved.
58
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