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HI-8581CJI 参数 Datasheet PDF下载

HI-8581CJI图片预览
型号: HI-8581CJI
PDF下载: 下载PDF文件 查看货源
内容描述: ARINC- 429线路驱动器和双接收机 [ARINC 429 LINE DRIVER AND DUAL RECEIVER]
分类和应用: 驱动器微控制器和处理器串行IO控制器通信控制器外围集成电路接收机数据传输时钟
文件页数/大小: 15 页 / 481 K
品牌: HOLTIC [ HOLT INTEGRATED CIRCUITS ]
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HI-8581  
June 2001  
GENERAL DESCRIPTION  
FEATURES  
! ARINC specification 429 compatible  
The HI-8581 device from Holt Integrated Circuits is a silicon  
gate CMOS device for interfacing a 16-bit parallel data bus  
directly to the ARINC 429 serial bus. The device provides  
two receivers, an independent transmitter and line driver  
capability in a single package. The receiver input circuitry  
and logic are designed to meet the ARINC 429  
specifications for loading, level detection, timing, and  
protocol. The transmitter section provides the ARINC 429  
communication protocol and the line driver circuits provide  
the ARINC 429 output levels.  
! Direct receiver and transmitter interface to  
ARINC bus in a single device.  
! 16-Bit parallel data bus.  
! Timing control 10 times the data rate  
! Selectable data clocks  
! Receiver error rejection per ARINC  
specification 429  
! Automatic transmitter data timing  
! Self test mode  
The 16-bit parallel data bus exchanges the 32-bit ARINC  
data word in two steps when either loading the transmitter  
or interrogating the receivers. The data bus interfaces with  
CMOS and TTL.  
! Parity functions  
! Low power  
Timing of all the circuitry begins with the master clock input,  
CLK. For ARINC 429 applications, the master clock  
frequency is 1 MHz.  
! Industrial & full military temperature ranges  
PIN CONFIGURATION (Top View)  
Each independent receiver monitors the data stream with a  
sampling rate 10 times the data rate. The sampling rate is  
software selectable at either 1MHz or 125KHz. The results  
of a parity check are available as the 32nd ARINC bit. The  
HI-8581 examines the null and data timings and will reject  
erroneous patterns. For example, with a 125 KHz clock  
selection, the data frequency must be between 10.4 KHz  
and 15.6 KHz.  
The transmitter has a First In, First Out (FIFO) memory to  
store 8 ARINC words for transmission. The data rate of the  
transmitter is software selectable by dividing the master  
clock, CLK, by either 10 or 80. The master clock is used to  
set the timing of the ARINC transmission within the required  
resolution.  
429DI2(B) - 1  
D/R1 - 2  
D/R2 - 3  
SEL - 4  
33 - ENTX  
32 - N/C  
31 - V+  
30 - TXB(OUT)  
29 - TXA(OUT)  
28 - V-  
27 - GND  
26 - TX/R  
25 - PL2  
EN1 - 5  
EN2 - 6  
HI-8581PQI  
&
HI-8581PQT  
BD15 - 7  
BD14 - 8  
BD13 - 9  
BD12 - 10  
BD11 - 11  
24 - PL1  
23 - BD00  
APPLICATIONS  
! Avionics data communication  
! Serial to parallel conversion  
! Parallel to serial conversion  
(See page 13 for additional pin configurations)  
HOLT INTEGRATED CIRCUITS  
(DS8581 Rev. A)  
1
06/01