HI-8581
SIGNAL
VCC
FUNCTION
POWER
POWER
POWER
INPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
I/O
DESCRIPTION
+5V ±5%
V+
+9.5V to +12.6V
-9.5V to -12.6V
V-
429DI1 (A)
429DI1 (B)
429DI2 (A)
429DI2 (B)
D/R1
ARINC receiver 1 positive input
ARINC receiver 1 negative input
ARINC receiver 2 positive input
ARINC receiver 2 negative input
Receiver 1 data ready flag
D/R2
Receiver 2 data ready flag
SEL
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1
Data Bus control, enables receiver 1 data to outputs
EN2
Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15
BD14
BD13
BD12
BD11
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
0 V
I/O
I/O
I/O
I/O
BD10
BD09
BD08
BD07
BD06
GND
I/O
I/O
I/O
I/O
I/O
POWER
I/O
BD05
BD04
BD03
BD02
BD01
BD00
TX/R
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
Data Bus
I/O
I/O
I/O
I/O
I/O
OUTPUT
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
After transmission and FIFO empty.
PL1
PL2
INPUT
INPUT
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
Line driver output - A side
TXA(OUT)
TXB(OUT)
ENTX
OUTPUT
OUTPUT
INPUT
Line driver output - B side
Enable Transmission
CWSTR
CLK
INPUT
Clock for control word register
INPUT
Master Clock input
TX CLK
MR
OUTPUT
INPUT
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
2
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
