HI-3210
HOST SERIAL PERIPHERAL INTERFACE
In the HI-3210, internal RAM and registers occupy a (32K +
128) x 8 address space. The lowest 32K addresses access
RAM locations and the remaining addresses access
registers. Timing is identical for register operations and
RAM operations via the serial peripheral interface, and
read and write operations have likewise identical timing.
SCK, and output data for each device changes on the
falling edge. These are known as SPI Mode 0 (CPHA = 0,
CPOL = 0) and SPI Mode 3 (CPHA= 1, CPOL = 1). Be sure
to set the host SPI logic for one of these modes.
As seen in Figure 1, the difference between SPI Modes 0
and 3 is the idle state for the SCK signal. There is no
configuration setting in the HI-3210 to select SPI Mode 0 or
Mode 3 because compatibility is automatic. Beyond this
point, the HI-3210 data sheet only shows the SPI Mode 0
SCK signal in timing diagrams.
Host access is only allowed when the part is READY or in
SAFE mode. NOTE: writes will be blocked and reads will
return the Master Status Register value until either of these
modes occur.
The SPI protocol transfers serial data as 8-bit bytes. Once
CS chip select is asserted, the next 8 rising edges on SCK
latch input data into the master and slave devices, starting
with each byte’s most-significant bit. The HI-3210 SPI can
be clocked at 20 MHz.
Serial Peripheral Interface (SPI) Basics
The HI-3210 uses an SPI synchronous serial interface for
host access to registers and RAM. Host serial
communication is enabled through the Chip Select (CS)
pin, and is accessed via a three-wire interface consisting of
Serial Data Input (SI) from the host, Serial Data Output
(SO) to the host and Serial Clock (SCK). All programming
cycles are completely self-timed, and no erase cycle is
required before write.
Multiple bytes may be transferred when the host holds CS
low after the first byte transferred, and continues to clock
SCK in multiples of 8 clocks. A rising edge on CS chip
select terminates the serial transfer and reinitializes the
HI-3210 SPI for the next transfer. If CS goes high before a
full byte is clocked by SCK, the incomplete byte clocked
into the device SI pin is discarded.
The SPI (Serial Peripheral Interface) protocol specifies
master and slave operation; the HI-3210 Host CPU
interface operates as an SPI slave.
In the general case, both master and slave simultaneously
send and receive serial data (full duplex) as shown in
Figure 1 below. When the HI-3210 is sending data on SO
during read operations, activity on its SI input is ignored.
Figures 2 and 3 show actual behavior for the HI-3210 SO
output.
The SPI protocol defines two parameters, CPOL (clock
polarity) and CPHA (clock phase). The possible CPOL-
CPHA combinations define four possible "SPI Modes."
Without describing details of the SPI modes, the HI-3210
operates in the two modes where input data for each
device ( master and slave) is clocked on the rising edge of
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
SCK (SPI Mode 0)
SCK (SPI Mode 3)
SI
MSB
LSB
LSB
High Z
High Z
SO
MSB
CS
FIGURE 1. Generalized Single-Byte Transfer Using SPI Protocol, SCK is Shown for SPI Modes 0 and 3
HOLT INTEGRATED CIRCUITS
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HOLTIC [ HOLT INTEGRATED CIRCUITS ]
