HI-3210
f. Write then read and verify 0x0F
g. Write then read and verify 0xF0
h. Write then read and verify 0x00
I. Write then read and verify 0xFF
j. Write 0xFF then increment RAM address and go to step (a)
5. Write an incrementing pattern into sequential RAM locations from 0x0000 to 0x7FFF
6. Read each memory location from 0x0000 to 0x7FFF and verify the contents
7. Write 1s complement of each cell’s current contents, into each RAM location (same addr range)
8. Read each memory location and verify the contents
3
RBSTRT RAM BISTStart.
Writing logic 1 to this bit initiates the RAM BIST test selected by register bits RBSEL2:0. The RBSTRT
bit can only be set in MODE2:0 = 0x04. This bit is automatically cleared upon test completion.
Register bits 1:0 indicate fail / pass test result.
2
1
---------
Not Used.
RBFAIL
RAM BISTFail.
Device logic asserts this bit when failure occurs while performing the selected RAM test. This bit is
automatically cleared when RBSTRT bit 3 is set. When BIST failure occurs, a clue to the failing RAM
address can be read at register addresses 0x8071 and 0x8072. For speed, the RAM BIST
concurrently tests four consecutive RAM addresses in parallel. If a test failure occurs, register
addresses 0x8071 and 0x8072 can be used to determine the four RAM addresses tested.
0
RBPASS RAM BISTPass.
Device logic asserts this bit when the selected RAM test completes without error. This bit is
automatically cleared when RBSTRTbit 3 is set.
BISTFL
LOWER BIST FAIL ADDRESS REGISTER
(Address 0x8071)
7
6
5
4
3
2
1
0
LSB
MSB
BISTFH
X
X
UPPER BIST FAIL ADDRESS REGISTER
(Address 0x8072)
15 14 13 12 11 10
MSB
9
8
LSB
HOLT INTEGRATED CIRCUITS
31
HOLTIC [ HOLT INTEGRATED CIRCUITS ]
