HT48R063/064/065/066/0662/067
¨
HT48R0662/HT48R067
Bit
Name
R/W
7
PCFG
R/W
0
6
PFDCS
R/W
0
5
PWMSEL
R/W
4
PWMC1
R/W
0
3
PWMC0
R/W
0
2
PFDC
R/W
0
1
LXTLP
R/W
0
0
CLKMOD
R/W
POR
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Note:
PCFG: pin-out remapping configuration
0: INT/TC0/PFD pin shared with PA3/PA2/PA1
1: INT/TC0/PFD pin shared with PB5/PB4/PB3
PFDCS: PFD clock source
0: timer0
1: timer1
PWMSEL: PWM type selection
0: 6+2
1: 7+1
PWMC1: I/O or PWM1 control
0: I/O
1: PWM1 output
PWMC0: I/O or PWM0 control
0: I/O
1: PWM0 output
PFDC: I/O or PFD control
0: I/O
1: PFD output
LXTLP: LXT oscillator low power control function
0: LXT oscillator start-up mode
1: LXT oscillator Low Power mode
CLKMOD: system clock mode selection.
0: High speed - HIRC/ERC/HXT used as system clock
1: Low speed - LXT used as system clock, internal HIRC/ERC/HXT stopped.
If PWM0/1/2 output is selected by PWMC0/1/2 bit, fTP comes always from fSYS
.
(fTP is the clock source for timer0/2 , time base and PWM)
·
CTRL1 Register
Bit
7
6
INTEG0
R/W
0
5
TBSEL1
R/W
0
4
TBSEL0
R/W
0
3
2
1
0
Name
R/W
INTEG1
R/W
1
WDTEN3 WDTEN2 WDTEN1 WDTEN0
R/W
1
R/W
0
R/W
1
R/W
0
POR
Bit 7, 6
INTEG1, INTEG0: External interrupt edge type
00: disable
01: rising edge trigger
10: falling edge trigger
11: dual edge trigger
Bit 5, 4
TBSEL1, TBSEL0: Time base period selection
00: 210 ´ (1/fTP
01: 211 ´ (1/fTP
10: 212 ´ (1/fTP
11: 213 ´ (1/fTP
)
)
)
)
Bit 3~0
Note:
WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable
1010: WDT disabled
Other values: WDT enabled - Recommended value is 0101
If the ²watchdog timer enable² is configuration option is selected, then the watchdog timer will
always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.
The WDT is only disabled when both the WDT configuration option is disabled and when bits
WDTEN3~WDTEN0=1010.
The WDT is enabled when either the WDT configuration option is enabled or when bits
WDTEN3~WDTEN0¹1010.
Rev. 1.10
23
June 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
