HT48R063/064/065/066/0662/067
Ta=25°C
Test Conditions
Conditions
¾
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
fLXT
System Clock (LXT)
32768
¾
Hz
¾
¾
0
¾
4000
8000
12000
15
2.2V~5.5V
3.0V~5.5V
4.5V~5.5V
kHz
kHz
kHz
kHz
kHz
Timer Input Frequency
(TCn)
fTIMER
0
¾
¾
0
¾
3V
5V
¾
5
10
¾
fLIRC
LIRC Oscillator
6.5
1
13
19.5
¾
¾
¾
tRES
External Reset Low Pulse Width
¾
ms
tSYS
tSYS
tSYS
For HXT/LXT
1024
2
¾
¾
¾
1
¾
tSST
System Start-up time Period
¾
¾
For ERC/IRC
(By configuration option)
1024
¾
¾
tINT
Interrupt Pulse Width
¾
¾
¾
¾
¾
¾
¾
ms
ms
ms
tLVR
Low Voltage Width to Reset
0.25
¾
1
2
RESTD Reset Delay Time
100
¾
Note: 1. tSYS=1/fSYS
2. *For fERC, as the resistor tolerance will influence the frequency a precision resistor is recommended.
3. For the HT48R064 device, the fERC parameter is not applicable.
4. For the HT48R064 device, the HIRC support 4MHz only and fHIRC parameter of (5V, 3.0V~5.5V) is
applicable.
5. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should
be connected between VDD and VSS and located as close to the device as possible.
Power-on Reset Characteristics
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
VDD
Conditions
VDD Start Voltage to Ensure
Power-on Reset
VPOR
RRVDD
tPOR
100
¾
mV
V/ms
ms
¾
¾
¾
0.035
1
¾
¾
¾
VDD raising rate to Ensure
Power-on Reset
¾
¾
¾
¾
Minimum Time for VDD Stays at
¾
V
POR to Ensure Power-on Reset
V
D
D
t
P
O
R
R
V
R
D
D
V
P
O
R
T
i
m
Rev. 1.10
12
June 9, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
