HT48R063B/064B/065B/066B
PFD Function
the Port A control register PAC, to setup the PFD pins as
outputs. If only one pin is setup as an output, the other
pin can still be used as a normal data input pin. How-
ever, if both pins are setup as inputs then the PFD will
not function. For devices with dual outputs the PFD out-
puts will only be activated if bit PA0 is set high. For de-
vices with a single PFD output, bit PA1 must be set high
to activate the PFD. These output data bits can be used
as the on/off control bit for the PFD outputs. Note that
the PFD outputs will all be low if the output data bit is
cleared to zero.
The Programmable Frequency Divider provides a
means of producing a variable frequency output suitable
for applications, such as piezo-buzzer driving or other
interfaces requiring a precise frequency generator.
Depending upon which device is used, there is either a
single output, PFD, or a complimentary output pair, PFD
and PFD. As the pins are shared with I/O pins, the func-
tion is selected using the CTRL0 register. Note that the
PFD pin is the inverse of the PDF pin generating a com-
plementary output and supplying more power to con-
nected interfaces such as buzzers. The PFDEN[1:0] in
CTRL0 register can select a single PFD pin or the com-
plimentary pair PFD and PFD for those devices with
dual outputs.
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very pre-
cise values of frequency can be generated.
I/O Interfacing
The Timer/Event Counter overflow signal is the clock
source for the PFD function, which is controlled by
PFDCS bit in CTRL0. For applicable devices the clock
source can come from either Timer/Event Counter 0 or
Timer/Event Counter 1. The output frequency is con-
trolled by loading the required values into the timer
prescaler and timer registers to give the required divi-
sion ratio. The counter will begin to count-up from this
preload register value until full, at which point an over-
flow signal is generated, causing both the PFD and PFD
outputs to change state. The counter will then be auto-
matically reloaded with the preload register value and
continue counting-up.
The Timer/Event Counter, when configured to run in the
event counter or pulse width capture mode, requires the
use of an external timer pin for its operation. As this pin
is a shared pin it must be configured correctly to ensure
that it is setup for use as a Timer/Event Counter input
pin. This is achieved by ensuring that the mode select
bits in the Timer/Event Counter control register, select
either the event counter or pulse width capture mode.
Additionally the corresponding Port Control Register bit
must be set high to ensure that the pin is setup as an in-
put. Any pull-high resistor connected to this pin will re-
main valid even if the pin is used as a Timer/Event
Counter input.
If the CTRL0 register has selected the PFD function,
then for both PFD outputs to operate, it is essential for
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PFD Function - Complementary Outputs
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PFD Function - Single Output
Rev. 1.00
42
April 7, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
