HT48R063B/064B/065B/066B
·
TMR0C Register
Bit
7
6
T0M0
R/W
0
5
4
T0ON
R/W
0
3
T0EG
R/W
1
2
T0PSC2
R/W
0
1
T0PSC1
R/W
0
0
T0PSC0
R/W
0
Name
R/W
T0M1
R/W
0
T0S
R/W
0
POR
Bit 7,6
T0M1, T0M0: Timer0 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
T0S: timer clock source
0: fSYS
1: LXT oscillator
T0S selects the clock source for fTP which is provided for Timer 0, Timer 2, the Time-Base and
the PWM. If the PWM is enabled, then fSYS will be selected, overriding the T0S selection.
Bit 4
Bit 3
T0ON: Timer/event counter counting enable
0: disable
1: enable
T0EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse Width Capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
T0PSC2, T0PSC1, T0PSC0: Timer prescaler rate selection
Timer internal clock=
000: fTP
001: fTP/2
010: fTP/4
011: fTP/8
100: fTP/16
101: fTP/32
110: fTP/64
111: fTP/128
·
TMR1C Register
Bit
7
6
T1M0
R/W
0
5
4
T1ON
R/W
0
3
T1EG
R/W
1
2
1
0
Name
R/W
T1M1
R/W
0
T1S
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7,6
T1M1, T1M0: Timer1 operation mode selection
00: no mode available
01: event counter mode
10: timer mode
11: pulse width capture mode
Bit 5
Bit 4
Bit 3
T1S: timer clock source
0: fSYS/4
1: LXT oscillator
T1ON: Timer/event counter counting enable
0: disable
1: enable
T1EG:
Event counter active edge selection
0: count on raising edge
1: count on falling edge
Pulse width capture active edge selection
0: start counting on falling edge, stop on rasing edge
1: start counting on raising edge, stop on falling edge
Bit 2~0
unimplemented, read as ²0²
Rev. 1.00
39
April 7, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
