Preliminary
HT48R06A-1
CLR WDT1
Preclear watchdog timer
Description
The TD, PD flags, WDT and the WDT Prescaler has cleared (re-counting
from zero), if the other preclear WDT instruction has been executed. Only ex-
ecution of this instruction without the other preclear instruction just sets the
indicated flag which implies this instruction has been executed and the TO
and PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2 TC1 TO PD OV
0* 0*
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT2
Preclear watchdog timer
Description
The TO, PD flags, WDT and the WDT Prescaler are cleared (re-counting
from zero), if the other preclear WDT instruction has been executed. Only ex-
ecution of this instruction without the other preclear instruction, sets the in-
dicated flag which implies this instruction has been executed and the TO and
PD flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2 TC1 TO PD OV
0* 0*
Z
AC
C
¾
¾
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1's comple-
ment). Bits which previously contained a one are changed to zero and
vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2 TC1 TO PD OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
30
February 25, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
