Preliminary
HT48R06A-1
Instruction
Cycle
Flag
Affected
Mnemonic
Table Read
Description
TABRDC [m] Read ROM code (current page) to data memory and
TBLH
TABRDL [m] Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
Miscellaneous
NOP
CLR [m]
SET [m]
No operation
Clear data memory
1
1(1)
1(1)
1
None
None
None
Set data memory
Clear watchdog timer
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
TO,PD
TO(4),PD(4)
TO(4),PD(4)
None
Pre-clear watchdog timer
Pre-clear watchdog timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1
1(1)
1
None
TO,PD
1
Note: x: 8 bits immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1): If a loading to the PCL register occurs, the execution cycle of instructions will be delayed
one more cycle (four system clocks).
(2): If a skipping to next instruction occurs, the execution cycle of instructions will be delayed
one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3)
:
(1) and (2)
(4): The flags may be affected by the execution status. If the watchdog timer is cleared by
executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared.
Otherwise the TO and PD flags remain unchanged.
26
February 25, 2000
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
