HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
PWM Operation
A single register, known as PWMn and located in the Data Memory is assigned to each Pulse
Width Modulator channel. It is here that the 8-bit value, which represents the overall duty
cycle of one modulation cycle of the output waveform, should be placed. To increase the PWM
modulation frequency, each modulation cycle is subdivided into two or four individual modulation
subsections, known as the 7+1 mode or 6+2 mode respectively. The required mode and the on/
off control for each PWM channel is selected using the CTRL0 and CTRL2 registers. Note that
when using the PWM, it is only necessary to write the required value into the PWMn register
and select the required mode setup and on/off control using the CTRL0 and CTRL2 registers, the
subdivision of the waveform into its sub-modulation cycles is implemented automatically within
the microcontroller hardware. The PWM clock source is the system clock fSYS. This method of
dividing the original modulation cycle into a further 2 or 4 sub-cycles enable the generation of
higher PWM frequencies which allow a wider range of applications to be served. The difference
between what is known as the PWM cycle frequency and the PWM modulation frequency should
be understood. As the PWM clock is the system clock, fSYS, and as the PWM value is 8-bits wide,
the overall PWM cycle frequency is fSYS/256. However, when in the 7+1 mode of operation the
PWM modulation frequency will be fSYS/128, while the PWM modulation frequency for the 6+2
mode of operation will be fSYS/64.
PWM Modulation
PWM Cycle Frequency
PWM Cycle Duty
fSYS/ꢄ4 foꢁ (ꢄ+ꢃ) bits mode
fSYS/1ꢃ8 foꢁ (7+1) bits mode
fSYS/ꢃ5ꢄ
[PWM]/ꢃ5ꢄ
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit PWM register, has 256 clock periods.
However, in the 6+2 PWM mode, each PWM cycle is subdivided into four individual sub-cycles
known as modulation cycle 0 ~ modulation cycle 3, denoted as i in the table. Each one of these
four sub-cycles contains 64 clock cycles. In this mode, a modulation frequency increase of four
is achieved. The 8-bit PWM register value, which represents the overall duty cycle of the PWM
waveform, is divided into two groups. The first group which consists of bit2~bit7 is denoted here
as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In the
6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the
following table.
DC
Parameter
AC (0~3)
(Duty Cycle)
DC+1
ꢄ4
i < AC
Modꢀlation cꢂcle i
(i=0~3)
DC
ꢄ4
≧
i
AC
6+2 Mode Modulation Cycle Values
The following diagram illustrates the waveforms associated with the 6+2 mode of PWM operation.
It is important to note how the single PWM cycle is subdivided into 4 individual modulation
cycles, numbered from 0~3 and how the AC value is related to the PWM value.
Rev. 1.00
58
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HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
