HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate
as an event counter input pin, two things have to happen. The first is to ensure that the Operating
Mode Select bits in the Timer Control Register place the Timer/Event Counter in the Event
Counting Mode, the second is to ensure that the port control register configures the pin as an
input. It should be noted that in the event counting mode, even if the is in the Idle/Sleep Mode, the
Timer/Event Counter will continue to record externally changing logic events on the timer input
TCn pin. As a result when the timer overflows it will generate a timer interrupt and corresponding
wake-up source.
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Timer Mode Timing Chart
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Event Counter Mode Timing Chart (TnEG=1)
Pulse Width Capture Mode
In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses
applied to the external timer pin. To operate in this mode, the Operating Mode Select bit pair,
TnM1/TnM0, in the Timer Control Register must be set to the correct value as shown.
Contꢁol Registeꢁ Opeꢁating Mode
Bit7
Bit6
Select Bits foꢁ the Pꢀlse Width Captꢀꢁe Mode
1
1
In this mode the internal clock, fSYS , fSYS/4 or the LXT, is used as the internal clock for the 8-bit
Timer/Event Counter. However, the clock source, fSYS, for the 8-bit timer is further divided by a
prescaler, the value of which is determined by the Prescaler Rate Select bits TnPSC2~TnPSC0,
which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control Register
have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can be set high
to enable the Timer/Event Counter, however it will not actually start counting until an active edge
is received on the external timer pin.
If the Active Edge Select bit TnEG, which is bit 3 of the Timer Control Register, is low, once a
high to low transition has been received on the external timer pin, the Timer/Event Counter will
start counting until the external timer pin returns to its original high level. At this point the enable
bit will be automatically reset to zero and the Timer/Event Counter will stop counting. If the
Active Edge Select bit is high, the Timer/Event Counter will begin counting once a low to high
transition has been received on the external timer pin and stop counting when the external timer
pin returns to its original low level. As before, the enable bit will be automatically reset to zero and
the Timer/Event Counter will stop counting. It is important to note that in the pulse width capture
Mode, the enable bit is automatically reset to zero when the external control signal on the external
timer pin returns to its original level, whereas in the other two modes the enable bit can only be
reset to zero under program control.
Rev. 1.00
53
�anꢀaꢁꢂ ꢃꢄꢅ ꢃ011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
