HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
To choose which of the three modes the timer is to operate in, either in the timer mode, the event
counting mode or the pulse width capture mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair TnM1/TnM0, must be set to the required logic levels.
The timer-on bit, which is bit 4 of the Timer Control Register and known as TnON, provides the
basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing
the bit stops the counter. Bits 0~2 of the Timer Control Register determine the division ratio of the
input clock prescaler. The prescaler bit settings have no effect if an external clock source is used.
If the timer is in the event count or pulse width capture mode, the active transition edge level type
is selected by the logic level of bit 3 of the Timer Control Register which is known as TnEG. The
TnS bit selects the internal clock source if used.
Timer Mode
In this mode, the Timer/Event Counter can be utilised to measure fixed time intervals, providing
an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode,
the Operating Mode Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the
correct value as shown.
Contꢁol Registeꢁ Opeꢁating Mode
Select Bits foꢁ the Timeꢁ Mode
Bit7
Bit6
1
0
In this mode the internal clock is used as the timer clock. The timer input clock source is either
fSYS, fSYS/4 or the LXT oscillator. However, this timer clock source is further divided by a prescaler,
the value of which is determined by the bits TnPSC2~TnPSC0 in the Timer Control Register.
The timer-on bit, TnON must be set high to enable the timer to run. Each time an internal clock
high to low transition occurs, the timer increments by one; when the timer is full and overflows,
an interrupt signal is generated and the timer will reload the value already loaded into the preload
register and continue counting. A timer overflow condition and corresponding internal interrupt is
one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the
ETnI bits of the INTCn register are reset to zero.
Event Counter Mode
In this mode, a number of externally changing logic events, occurring on the external timer TCn
pin, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode
Select bit pair, TnM1/TnM0, in the Timer Control Register must be set to the correct value as
shown.
Contꢁol Registeꢁ Opeꢁating Mode
Bit7
Bit6
Select Bits foꢁ the Event Coꢀnteꢁ Mode
0
1
In this mode, the external timer TCn pin, is used as the Timer/Event Counter clock source,
however it is not divided by the internal prescaler. After the other bits in the Timer Control
Register have been setup, the enable bit TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit, TnEG, which is
bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time the
external timer pin receives a low to high transition. If the TnEG is high, the counter will increment
each time the external timer pin receives a high to low transition. When it is full and overflows,
an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded
into the preload register and continue counting. The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the corresponding Interrupt Control Register, is reset
to zero.
Rev. 1.00
5ꢃ
�anꢀaꢁꢂ ꢃꢄꢅ ꢃ011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
