HT46R064G/065G/0662G
Enhanced A/D Type 8-Bit OTP MCU with OPA
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked by
resetting the EMI bit.
HT46R064G
Interrupt Source
Priority
Vector
04H
External Interrupt
1
2
3
4
Timer/Event Counter 0 Overflow
A/D Conversion Complete
Time Base Overflow
08H
10H
14H
Multi-function interrupt
5
18H
(Comparator, OPA0, OPA1)
HT46R065G/HT46R0662G
Interrupt Source
Priority
Vector
04H
External Interrupt
1
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
A/D Conversion Complete
Time Base Overflow
2
3
4
5
08H
0CH
10H
14H
Multi-function interrupt
6
18H
(Comparator, OPA0, OPA1)
In cases where both external and internal interrupts are enabled and where an external and internal in-
terrupt occurs simultaneously, the external interrupt will always have priority and will therefore be
serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent
simultaneous occurrences.
Rev. 1.00
95
March 3, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
