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HT46R0662G 参数 Datasheet PDF下载

HT46R0662G图片预览
型号: HT46R0662G
PDF下载: 下载PDF文件 查看货源
内容描述: 增强A / D型8位OTP MCU与OPA [Enhanced A/D Type 8-Bit OTP MCU with OPA]
分类和应用:
文件页数/大小: 136 页 / 748 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R064G/065G/0662G  
Enhanced A/D Type 8-Bit OTP MCU with OPA  
Interrupts  
Interrupts are an important part of any microcontroller system. When an external event or an internal  
function such as a Timer/Event Counter or Time Base requires microcontroller attention, their  
corresponding interrupt will enforce a temporary suspension of the main program allowing the  
microcontroller to direct attention to their respective needs.  
The devices contain a single external interrupt and multiple internal interrupts. The external interrupt  
is controlled by the action of the external interrupt pin, while the internal interrupts are controlled by  
the various functions such as Timer/Event Counters and Time Base overflow, etc.  
Interrupt Register  
Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by  
using the registers, INTC0 and INTC1. By controlling the appropriate enable bits in the registers each  
individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding  
request flag will be set by the microcontroller. The global enable control bit if cleared to zero will  
disable all interrupts.  
INTC0 Register - HT46R064G  
Bit  
Name  
R/W  
7
6
5
4
3
2
1
INTE  
R/W  
0
0
T0F  
R/W  
0
INTF  
R/W  
0
T0E  
R/W  
0
EMI  
R/W  
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR  
Bit 7~6  
Bit 5  
unimplemented, read as ²0²  
T0F: Timer/Event Counter 0 interrupt request flag  
0: inactive  
1: active  
Bit 4  
INTF: External interrupt request flag  
0: inactive  
1: active  
Bit 3  
Bit 2  
unimplemented, read as ²0²  
T0E: Timer/Event Counter 0 interrupt enable  
0: disable  
1: enable  
Bit 1  
Bit 0  
INTE: external interrupt enable  
0: disable  
1: enable  
EMI: Master interrupt global enable  
0: disable  
1: enable  
Rev. 1.00  
91  
March 3, 2011