HT46R064G/065G/0662G
Enhanced A/D Type 8-Bit OTP MCU with OPA
Multi-function Interrupt
For a Multi-function interrupt to occur, the global interrupt enable bit, EMI, and the corresponding
multi-function interrupt enable bit, MFE, must first be set. An actual Multi-function interrupt will take
place when the Multi-function interrupt request flag, MFF, is set, a situation that will occur when
OPA0 or OPA1 output has a falling edge, or a Comparator output transition occurs. When the interrupt
is enabled, the stack is not full and a Multi-function interrupt request occurs, a subroutine call to the
Multi-function interrupt vector at location 18H, will take place. When the interrupt is serviced, the
Multi-function interrupt request flag, MFF, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. After the Multi-function took place, the programmer
can check what the interrupt source was by interrogating the request flags, A0F, A1F or CF within the
MFIC register.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until
the corresponding interrupt is serviced or until the request flag is cleared by a software instruction.
It is recommended that programs do not use the ²CALL subroutine² instruction within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in
some applications. If only one stack is left and the interrupt is not well controlled, the original control
sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine.
All of these interrupts have the capability of waking up the processor when in the Idle/Sleep Mode.
Only the Program Counter is pushed onto the stack. If the contents of the register or status register are
altered by the interrupt service program, which may corrupt the desired control sequence, then the
contents should be saved in advance.
SCOM Function for LCD
The HT46R065G and HT46R0662G devices have the capability of driving external LCD panels. The
common pins for LCD driving, SCOM0~SCOM3, are pin shared with certain pin on the PB0~PB3
port. The LCD signals (COM and SEG) are generated using the application program.
LCD Operation
An external LCD panel can be driven using this device by configuring the PB0~PB3 pins as common
pins and using other output ports lines as segment pins. The LCD driver function is controlled using
the SCOMC register which in addition to controlling the overall on/off function also controls the bias
voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage
levels for LCD 1/2 bias operation.
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LCD COM Bias
Rev. 1.00
97
March 3, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
