HT46R064D/065D/066D
Enhanced A/D Type 8-Bit OTP MCU with LED Driver
PCR Register - HT46R064D/HT46R065D
Bit
Name
R/W
7
6
5
4
3
PCR3
R/W
0
2
PCR2
R/W
0
1
PCR1
R/W
0
0
PCR0
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~4
Bit 3~0
unimplemented, read as ²0²
PCR3~PCR0: define I/O lines or analog inputs configuration to port
0: digital I/O. Pin is assigned as a I/O line or pin-shared function.
1: analog input. Pin is switched to analog input.
PCR Register - HT46R066D
Bit
7
6
5
PCR5
R/W
0
4
PCR4
R/W
0
3
PCR3
R/W
0
2
PCR2
R/W
0
1
PCR1
R/W
0
0
PCR0
R/W
0
Name
R/W
PCR7
PCR6
R/W
0
R/W
0
POR
Bit 7~0
PCR7~PCR0: define I/O lines or analog inputs configuration to port
0: digital I/O. Pin is assigned as a I/O line or pin-shared function.
1: analog input. Pin is switched to analog input.
The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process
is complete. This bit will be automatically set to ²0² by the microcontroller after a conversion cycle
has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt con-
trol register, and if the interrupts are enabled, an appropriate internal interrupt signal will be gener-
ated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal
interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be
used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative
method of detecting the end of an A/D conversion cycle.
The clock source for the A/D converter, which originates from the system clock fSYS, is first divided by
a division ratio, the value of which is determined by the ADCS1 and ADCS0 bits in the ACSR register.
Although the A/D clock source is determined by the system clock fSYS, and by bits ADCS1 and ADCS0,
there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum
value of permissible A/D clock period, tAD, is 0.5ms, care must be taken for system clock speeds in excess of
4MHz. For system clock speeds in excess of 4MHz, the ADCS1 and ADCS0 bits should not be set to ²00².
Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in
inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an
asterisk * show where, depending upon the device, special care must be taken, as the values may be less
than the specified minimum A/D Clock Period.
Rev. 1.00
60
January 12, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
