HT46R01/HT46R02/HT46R03
be assigned a zero value. The ADCR control register
also contains the PCR2~PCR0 bits which determine
which pins on Port A are used as analog inputs for the
A/D converter and which pins are to be used as normal
I/O pins. If the 3-bit address on PCR2~PCR0 has a
value of ²100² or higher, then all four pins, namely AN0,
AN1, AN2 and AN3 will all be set as analog inputs. Note
that if the PCR2~PCR0 bits are all set to zero, then all
the Port B pins will be setup as normal I/Os and the inter-
nal A/D converter circuitry will be powered off to reduce
the power consumption.
A/D Converter Data Registers - ADR, ADRL, ADRH
For the HT46R01 devices, which have an 8-bit A/D con-
verter, a single register, known as ADR, is used to store
the 8-bit analog to digital conversion value. For the re-
maining devices, which have a 9 or 12-bit A/D converter,
two registers are required, a high byte register, known
as ADRH, and a low byte register, known as ADRL. After
the conversion process takes place, these registers can
be directly read by the microcontroller to obtain the digit-
ised conversion value. For devices which use two A/D
Converter Data Registers, note that only the high byte
register ADRH utilises its full 8-bit contents. The low
byte register utilises only some of its 8-bit contents as it
contains only the lowest bits of the converted value.
The START bit in the ADCR register is used to start and
reset the A/D converter. When the microcontroller sets
this bit from low to high and then low again, an analog to
digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOCB bit in the ADCR register will be set high and
the analog to digital converter will be reset. It is the
START bit that is used to control the overall on/off opera-
tion of the internal analog to digital converter.
In the following tables, D0~D8 are the A/D conversion
data result bits.
Bit Bit Bit Bit Bit Bit Bit Bit
Register
7
6
5
4
3
2
1
0
ADR
D7 D6 D5 D4 D3 D2 D1 D0
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically cleared to zero by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detect-
ing the end of an A/D conversion cycle.
A/D Data Register - HT46R01
Bit Bit Bit Bit Bit Bit Bit Bit
Register
7
6
5
4
3
2
1
0
ADRL
ADRH
D0
¾
¾
¾
¾
¾
¾
¾
D8 D7 D6 D5 D4 D3 D2 D1
A/D Data Register - HT46R02
Bit Bit Bit Bit Bit Bit Bit Bit
Register
7
6
5
4
3
2
1
0
ADRL
D3 D2 D1 D0
¾
¾
¾
¾
ADRH D11 D10 D9 D8 D7 D6 D5 D4
A/D Data Register - HT46R03
A/D Converter Clock Source Register - ACSR
The clock source for the A/D converter, which originates
from the system clock fSYS, is first divided by a division
ratio, the value of which is determined by the bits
ADCS0 to ADCS2 in the ACSR register.
A/D Converter Control Register - ADCR
To control the function and operation of the A/D con-
verter, a control register known as ADCR is provided.
This 8-bit register defines functions such as the selec-
tion of which analog channel is connected to the internal
A/D converter, which pins are used as analog inputs and
which are used as normal I/Os as well as controlling the
start function and monitoring the A/D converter end of
conversion status.
Although the A/D clock source is determined by the sys-
tem clock fSYS, and by bits ADCS0 to ADCS2, there are
some limitations on the maximum A/D clock source
speed that can be selected. As the minimum value of
permissible A/D clock period, tAD, is 1us for all devices,
care must be taken for system clock speeds in excess of
1MHz. For system clock speeds in excess of 1MHz, the
ADCS0 to ADCS2 bits should not be set to give an A/D
clock period less than the specified minimum A/D clock
period which may result in inaccurate A/D conversion
values. Refer to the table for examples, where values
marked with an asterisk * show where special care must
be taken, as the values are less than the specified mini-
mum A/D Clock Period.
One section of this register contains the bits
ACS2~ACS0 which define the channel number. As each
of the devices contains only one actual analog to digital
converter circuit, each of the individual 4 analog inputs
must be routed to the converter. It is the function of the
ACS2~ACS0 bits in the ADCR register to determine
which analog channel is actually connected to the inter-
nal A/D converter. Note that the ACS2 bit must always
Rev. 1.00
27
September 21, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
