HT46R232/HT46C232
Note: 1: Write the I2C Bus address register (HADR) to define its own slave address.
2: Set HEN bit of I2C Bus control register (HCR) bit 0 to enable the I2C Bus.
Bit No. Label
Function
0~2
3
¾
Unused bit, read as ²0²
Enable/disable transmit acknowledge (0= acknowledge; 1= don¢t acknowledge)
TXAK
4
HTX Defines the transmit/receive mode (0= receive mode; 1= transmit)
5~6
7
¾
Unused bit, read as ²0²
HEN Enable/disable I2C Bus function (0= disable; 1= enable)
HCR (21H) Register
3: Set EHI bit of the interrupt control register 1 (INTC1) bit 0 to enable the I2C Bus interrupt.
Bit No. Label
Function
RXAK is cleared to ²0² when the master receives an 8-bit data and acknowledgment
at the 9th clock, RXAK is set to ²1² means not acknowledged.
0
1
RXAK
¾
Unused bit, read as ²0²
SRW is set to ²1² when the master wants to read data from the I2C Bus, so the slave
must transmit data to the master. SRW is cleared to ²0² when the master wants to
write data to the I2C Bus, so the slave must receive data from the master.
2
SRW
3~4
5
¾
Unused bit, read as ²0²
HBB is set to ²1² when I2C Bus is busy and HBB is cleared to ²0² means that the I2C
Bus is not busy.
HBB
HAAS is set to ²1² when the calling address has matched, and I2C Bus interrupt will
occur and HCF is set.
6
7
HAAS
HCF
HCF is cleared to ²0² when one data byte is being transferred, HCF is set to ²1² indi-
cating 8-bit data communication has been finished.
HSR (22H) Register
S
t
a
r
t
S
l
a
v
e
A
d
d
r
e
s
s
S
R
W
A
C
K
S
C
L
0
1
1
1
0
1
0
1
0
S
D
D
S
A
D
a
t
a
A
C
K
S
t
o
p
S
C
L
1
0
0
1
0
1
0
0
S
A
S
=
S
t
S
a
r
t
(
1
b
i
t
)
S
A
R
=
l
a
v
e
A
d
d
r
e
s
s
(
7
b
i
t
s
)
S
=
S
R
W
b
i
t
(
1
b
i
t
)
M
=
S
l
a
v
e
d
e
v
i
c
e
s
e
n
d
a
c
k
n
o
w
l
e
d
g
e
b
i
t
(
1
b
i
t
)
D
=
D
a
t
a
(
8
b
i
t
s
)
A
P
=
=
A
S
C
t
K
(
R
X
A
i
K
b
i
t
f
o
r
t
r
a
n
s
m
i
t
t
e
r
,
T
X
A
K
b
i
t
f
o
r
r
e
c
e
i
v
e
r
1
b
i
t
)
o
p
(
1
b
t
)
S
A
S
R
M
D
A
D
A
S
S
A
S
R
M
D
A
D
A
P
I2C Communication Timing Diagram
Rev. 1.50
25
January 21, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
