HT46R232/HT46C232
value from the stack. After a chip reset, the SP will point
to the top of the stack.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H). The
space before 40H is overlapping in each bank.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt is
serviced. This feature prevents stack overflow, allowing
the programmer to use the structure more easily. If the
stack is full and a ²CALL² is subsequently executed,
stack overflow occurs and the first entry will be lost (only
the most recent 8 return addresses are stored).
I
n
d
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c
t
A
d
d
r
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M
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M
s
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g
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r
0
0
0
0
1
H
H
P
0
I
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d
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c
t
A
d
d
r
s
s
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g
R
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g
i
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t
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r
1
0
2
H
P
1
0
3
H
0
4
H
Data Memory - RAM
A
C
C
0
5
H
P
C
L
0
6
H
The data memory (RAM) is designed with 231´8 bits,
and is divided into two functional groups, namely; spe-
cial function registers (39´8 bits) and general purpose
data memory (192´8 bits) most of which are read-
able/writeable, although some are read only.
T
B
L
P
0
7
H
T
B
L
H
0
8
H
0
9
H
0
0
A
B
H
H
S
T
A
T
U
S
I
N
T
C
0
The special function registers are overlapped in any
banks. Of the two types of functional groups, the special
function registers consist of an Indirect addressing reg-
ister 0 (00H), a Memory pointer register 0 (MP0;01H),
an Indirect addressing register 1 (02H), a Memory
pointer register 1 (MP1;03H), an Accumulator
(ACC;05H), a Program counter lower-order byte regis-
ter (PCL;06H), a Table pointer (TBLP;07H), a Table
higher-order byte register (TBLH;08H), a Status register
(STATUS;0AH), an Interrupt control register 0
(INTC0;0BH), a Timer/Event Counter 0 (TMR0H:0CH;
TMR0L:0DH), a Timer/Event Counter 0 control register
(TMR0C;0EH), a Timer/Event Counter 1 (TMR1H:0FH;
TMR1L:10H), a Timer/Event Counter 1 control register
(TMR1C; 11H), Interrupt control register 1 (INTC1;1EH),
PWM data register (PWM0;1AH, PWM1;1BH,
PWM2;1CH, PWM3;1DH), the I2C Bus slave address
register (HADR;20H), the I2C Bus control register
(HCR;21H), the I2C Bus status register (HSR;22H), the
I2C Bus data register (HDR;23H),the A/D result
lower-order byte register (ADRL;24H), the A/D result
higher-order byte register (ADRH;25H), the A/D control
register (ADCR;26H), the A/D clock setting register
(ACSR;27H), I/O registers (PA;12H, PB;14H, PC;16H,
PD;18H, PF; 28H) and I/O control registers (PAC;13H,
PBC;15H, PCC;17H, PDC;19H, PFC;29H). The remain-
ing space before the 40H is reserved for future ex-
panded usage and reading these locations will get
²00H². The space before 40H is overlapping in each
bank. The general purpose data memory, addressed
from 40H to FFH, is used for data and control informa-
tion under instruction commands.
0
0
C
D
H
H
T
M
R
0
H
T
M
R
0
L
0
E
H
T
T
M
M
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R
0
1
C
H
0
F
H
1
1
0
1
H
H
T
M
R
1
L
T
M
R
1
C
1
2
H
P
A
1
3
H
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C
1
4
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1
5
H
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6
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1
7
H
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1
8
H
D
1
9
H
1
1
A
B
H
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P
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W
W
W
W
M
M
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0
1
2
3
1
1
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1
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1
1
F
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2
2
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
8
9
H
A
D
R
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C
R
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S
R
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A
D
R
L
A
A
D
D
R
C
H
R
A
C
S
R
P
F
P
F
C
3
3
0
F
H
H
4
0
H
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0
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(
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F
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RAM Mapping
Rev. 1.50
8
January 21, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
