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HT45R37-A(28SSOP-A) 参数 Datasheet PDF下载

HT45R37-A(28SSOP-A)图片预览
型号: HT45R37-A(28SSOP-A)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 12MHz, CMOS, PDSO28]
分类和应用: 可编程只读存储器LTE微控制器光电二极管
文件页数/大小: 100 页 / 666 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT45R37  
Clearing the Watchdog Timer  
time-out period may vary with temperature, VDD and  
process variations. As the clear instruction only resets  
the last stage of the divider chain, for this reason the ac-  
tual division ratio and corresponding Watchdog Timer  
time-out can vary by a factor of two. The exact division  
ratio depends upon the residual value in the Watchdog  
Timer counter before the clear instruction is executed.  
There are two methods of using software instructions to  
clear the Watchdog Timer, one of which must be chosen  
by configuration option. The first option is to use the sin-  
gle ²CLR WDT² instruction while the second is to use the  
two commands ²CLR WDT1² and ²CLR WDT2². For the  
first option, a simple execution of ²CLR WDT² will clear  
the WDT while for the second option, both ²CLR WDT1²  
and ²CLR WDT2² must both be executed to successfully  
clear the Watchdog Timer. Note that for this second op-  
tion, if ²CLR WDT1² is used to clear the Watchdog Timer,  
successive executions of this instruction will have no ef-  
fect, only the execution of a ²CLR WDT2² instruction will  
clear the Watchdog Timer. Similarly after the ²CLR  
WDT2² instruction has been executed, only a successive  
²CLR WDT1² instruction can clear the Watchdog Timer.  
If the fSYS/4 clock is used as the Watchdog Timer clock  
source, it should be noted that when the system enters  
the Power Down Mode, then the instruction clock is  
stopped and the Watchdog Timer will lose its protecting  
purposes. For systems that operate in noisy environ-  
ments, using the 32K_INT RC oscillator is strongly rec-  
ommended.  
Under normal program operation, a Watchdog Timer  
time-out will initialise a device reset and set the status bit  
TO. However, if the system is in the Power Down Mode,  
when a Watchdog Timer time-out occurs, the TO bit in  
the status register will be set and only the Program  
Counter and Stack Pointer will be reset. Three methods  
can be adopted to clear the contents of the Watchdog  
Timer. The first is an external hardware reset, which  
means a low level on the RES pin, the second is using  
the watchdog software instructions and the third is via a  
²HALT² instruction.  
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Watchdog Timer Software Control - MISC  
Rev. 1.20  
68  
February 25, 2011  
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