Section 4 Exception Handling
4.1
Overview
The H8/3437 Series recognizes two kinds of exceptions: interrupts and the reset. Table 4.1
indicates their priority and the timing of their hardware exception-handling sequence.
Table 4.1 Hardware Exception-Handling Sequences and Priority
Type of
Exception
Detection
Timing
Priority
Timing of Exception-Handling Sequence
High
Reset
Synchronized
with clock
The hardware exception-handling sequence begins
as soon as RES changes from low to high.
Interrupt
End of instruction When an interrupt is requested, the hardware
execution*
exception-handling sequence begins at the end of
the current instruction, or at the end of the current
hardware exception-handling sequence.
Low
Note: * Not detected after ANDC, ORC, XORC, and LDC instructions.
4.2Reset
4.2.1
Overview
A reset has the highest exception-handling priority. When the RES pin goes low or when there is a
watchdog timer reset (when the reset option is selected for watchdog timer overflow), all current
processing stops and the chip enters the reset state. The internal state of the CPU and the registers
of the on-chip supporting modules are initialized. The reset exception-handling sequence starts
when RES returns from low to high, or at the end of a watchdog reset pulse.
4.2.2
Reset Sequence
The reset state begins when RES goes low or a watchdog reset is generated. To ensure correct
resetting, at power-on the RES pin should be held low for at least 20 ms. In a reset during
operation, the RES pin should be held low for at least 10 system clock cycles. The watchdog reset
pulse width is always 518 system clocks. For the pin states during a reset, see appendix D, Pin
States.
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HITACHI [ HITACHI SEMICONDUCTOR ]
