Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by a reset, but is not initialized in the software standby mode.
Bit 0: RAME
Description
0
1
The on-chip RAM is disabled.
The on-chip RAM is enabled.
(Initial value)
3.3
Mode Control Register (MDCR)
Bit
7
6
5
4
3
2
1
0
EXPE*1
—
1
—
1
—
0
—
0
—
1
MDS1
MDS0
*2
*2
*2
Initial value
Read/Write
—
—
—
R/W*2
—
—
—
—
—
R
R
Notes: *1 H8/3437SF (S-mask model, single-power-supply on-chip flash memory version) only.
Otherwise, this is a reserved bit that is always read as 1.
*2 Determined by the mode pins (MD1 and MD0).
The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the
chip.
Bit 7—Expanded Mode Enable (EXPE): Functions only in the H8/3437SF (S-mask model,
single-power-supply on-chip flash memory version). For details, see section 21.1.6, Mode Control
Register (MDCR).
In models other than the H8/3437SF, this is a reserved bit that cannot be modified and is always
read as 1.
Bits 6 and 5—Reserved: These bits cannot be modified and are always read as 1.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bit 2—Reserved: This bit cannot be modified and is always read as 1.
Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the
mode pins (MD1 and MD0), thereby indicating the current operating mode of the chip. MDS1
corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode
control register is read, the levels at the mode pins (MD1 and MD0) are latched in these bits.
60
HITACHI [ HITACHI SEMICONDUCTOR ]
