3.2
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
SSBY
0
STS2
0
STS1
0
STS0
0
XRST
NMIEG
HIE
0
RAME
1
Initial value
Read/Write
1
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
The system control register (SYSCR) is an 8-bit register that controls the operation of the chip.
Bit 7—Software Standby (SSBY): Enables transition to the software standby mode. For details,
see section 22, Power-Down State.
On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1.
It can be cleared by writing 0.
Bit 7: SSBY
Description
0
1
The SLEEP instruction causes a transition to sleep mode.
(Initial value)
The SLEEP instruction causes a transition to software standby mode.
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During the
selected time the CPU and on-chip supporting modules continue to stand by. These bits should be
set according to the clock frequency so that the settling time is at least 8 ms. For specific settings,
see section 22.3.3, Clock Settling Time for Exit from Software Standby Mode.
•
ZTAT and Mask ROM Versions
Bit 6: STS2
Bit 5: STS1
Bit 4: STS0
Description
0
0
0
Settling time = 8,192 states
Settling time = 16,384 states
Settling time = 32,768 states
Settling time = 65,536 states
Settling time = 131,072 states
Unused
(Initial value)
1
1
0
1
1
0
1
—
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58
HITACHI [ HITACHI SEMICONDUCTOR ]
