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F-ZTAT Version
Bit 6: STS2
Bit 5: STS1
Bit 4: STS0
Description
0
0
0
Settling time = 8,192 states
Settling time = 16,384 states
Settling time = 32,768 states
Settling time = 65,536 states
Settling time = 131,072 states
Settling time = 1,024 states
Unused
(Initial value)
1
1
0
1
0
1
1
0
1
—
Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted.
If a period exceeding øp/1,024 (e.g. øp/2,048) is specified when selecting the 8-bit timer,
PWM timer, or watchdog timer clock, the counter in the timer will not count up normally
when 1,024 states is specified for the settling time. To avoid this problem, set the STS value
just before the transition to software standby mode (before executing the SLEEP
instruction), and re-set the value of STS2 to STS0 to a value from 000 to 100 directly after
software standby mode is cleared by an interrupt.
Bit 3—External Reset (XRST): Indicates the source of a reset. A reset can be generated by input
of an external reset signal, or by a watchdog timer overflow when the watchdog timer is used.
XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer
overflow.
Bit 3: XRST
Description
0
1
Reset was caused by watchdog timer overflow.
Reset was caused by external input.
(Initial value)
(Initial value)
Bit 2—NMI Edge (NMIEG): Selects the valid edge of the NMI input.
Bit 2: NMIEG
Description
0
1
An interrupt is requested on the falling edge of the NMI input.
An interrupt is requested on the rising edge of the NMI input.
Bit 1—Host Interface Enable (HIE): Enables or disables the host interface function. When
enabled, the host interface processes host-slave data transfers, operating in slave mode.
Bit 1: HIE
Description
0
1
The host interface is disabled.
The host interface is enabled (slave mode).
(Initial value)
59
HITACHI [ HITACHI SEMICONDUCTOR ]
