14.4
Interrupts
14.4.1 IBF1, IBF2
The host interface can request two interrupts to the slave CPU: IBF1 and IBF2. They are input
buffer full interrupts for input data registers IDR1 and IDR2 respectively. Each interrupt is
enabled when the corresponding enable bit is set (table 14.8).
Table 14.8 Input Buffer Full Interrupts
Interrupt
IBF1
Description
Requested when IBFIE1 is set to 1 and IDR1 is full
Requested when IBFIE2 is set to 1 and IDR2 is full
IBF2
14.4.2 HIRQ11, HIRQ1, and HIRQ12
In slave mode (when HIE = 1 in SYSCR), three bits in the port 4 data register (P4DR) can be used
as host interrupt request latches.
These three P4DR bits are cleared to 0 by the host processor’s read signal (IOR). If CS1 and HA
0
are low, when IOR goes low and the host reads ODR1, HIRQ1 and HIRQ12 are cleared to 0. If CS2
and HA0 are low, when IOR goes low and the host reads ODR2, HIRQ11 is cleared to 0. To
generate a host interrupt request, normally on-chip software writes 1 to the corresponding bit. In
processing the interrupt, the host’s interrupt-handling routine reads the output data register (ODR1
or ODR2), and this clears the host interrupt latch to 0.
Table 14.9 indicates how these bits are set and cleared. Figure 14.3 shows the processing in
flowchart form.
Table 14.9 Host Interrupt Set/Clear Conditions
Host Interrupt
Signal
Setting Condition
Clearing Condition
HIRQ11 (P43)
Slave CPU reads 0 from P4DR bit 3,
then writes 1
Slave CPU writes 0 in P4DR bit 3, or
host reads output data register 2
HIRQ1 (P44)
HIRQ12 (P45)
Slave CPU reads 0 from P4DR bit 4,
then writes 1
Slave CPU writes 0 in P4DR bit 4, or
host reads output data register 1
Slave CPU reads 0 from P4DR bit 5,
then writes 1
Slave CPU writes 0 in P4DR bit 5, or
host reads output data register 1
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HITACHI [ HITACHI SEMICONDUCTOR ]
