11.1.4 Register Configuration
Table 11.2 lists information on the watchdog timer registers.
Table 11.2 Register Configuration
Addresses
Write Read
Initial
Value
Name
Abbreviation
TCSR
R/W
Timer control/status register
Timer counter
R/(W)*
R/W
H'10
H'00
H'FFA8
H'FFA8
H'FFA8
H'FFA9
TCNT
Note: * Software can write a 0 to clear the status flag bits, but cannot write 1.
11.2
Register Descriptions
11.2.1 Timer Counter (TCNT)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal
clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count
overflows (changes from H'FF to H'00), an overflow flag (OVF) in TCSR is set to 1.
TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0.
Note: TCNT is more difficult to write to than other registers. See Section 11.2.4, Register
Access, for details.
223
HITACHI [ HITACHI SEMICONDUCTOR ]
