11.2.2 Timer Control/Status Register (TCSR)
Bit
7
OVF
0
6
WT/IT
0
5
4
—
1
3
2
1
CKS1
0
0
CKS0
0
TME
0
RST/NMI CKS2
Initial value
Read/Write
0
0
R/(W)*
R/W
R/W
—
R/W
R/W
R/W
R/W
Note: * Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.
TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and
performs other functions. (TCSR is write-protected by a password. See section 11.2.3, Register
Access, for details.)
Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are
initialized to 0 by a reset, but retain their values in the standby modes.
Bit 7—Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed.
Bit 7: OVF
Description
0
To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0
in this bit
(Initial value)
1
Set to 1 when TCNT changes from H'FF to H'00
Bit 6—Timer Mode Select (WT/IT): Selects whether to operate in watchdog timer mode or
interval timer mode. When TCNT overflows, an WOVF interrupt request is sent to the CPU in
interval timer mode. For watchdog timer mode, a reset or NMI interrupt is requested.
Bit 6: WT/IT
Description
0
1
Interval timer mode (WOVF request)
Watchdog timer mode (reset or NMI request)
(Initial value)
Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME
Description
0
1
TCNT is initialized to H'00 and stopped
TCNT runs and requests a reset or an interrupt when it overflows
(Initial value)
224
HITACHI [ HITACHI SEMICONDUCTOR ]
