Port 5 Data Direction Register (P5DDR)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
1
0
P52DDR P51DDR P50DDR
Initial value
Read/Write
0
0
0
—
—
—
—
—
W
W
W
P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin
functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this bit
is cleared to 0.
P5DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P5DDR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode
it retains its existing values, so if a transition to software standby mode occurs while a P5DDR bit
is set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI will
be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR and
P5DR.
Port 5 Data Register (P5DR)
Bit
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
P52
0
1
P51
0
0
P50
0
Initial value
Read/Write
—
—
—
—
—
R/W
R/W
R/W
P5DR is an 8-bit register that stores data for pins P52 to P50. Bits 7 to 3 are reserved. They cannot
be modified, and are always read as 1.
When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless
of the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is obtained.
This also applies to pins used as SCI pins.
P5DR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode it
retains its existing values.
127
HITACHI [ HITACHI SEMICONDUCTOR ]
