Pin Wait Mode: In all accesses to external addresses, the number of wait states (TW) selected by
bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the
last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait
states continue to be inserted until the WAIT signal goes high.
Pin wait mode is useful for inserting four or more wait states, or for inserting different numbers of
wait states for different external devices.
Figure 5.3 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait
state is inserted by WAIT input.
Inserted by Inserted by
wait count
WAIT signal
T
1
T2
TW
TW
T3
ø
*
*
WAIT pin
Address bus
External address
AS
RD
Read
access
Read data
Data bus
WR
Write
access
Data bus
Write data
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 5.3 Pin Wait Mode
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HITACHI [ HITACHI SEMICONDUCTOR ]
