5.1.3
Input/Output Pins
Table 5.1 summarizes the wait-state controller’s input pin.
Table 5.1 Wait-State Controller Pins
Name
Abbreviation
I/O
Function
Wait
WAIT
Input
Wait request signal for access to external addresses
5.1.4
Register Configuration
Table 5.2 summarizes the wait-state controller’s register.
Table 5.2 Register Configuration
Address
Name
Abbreviation
R/W
Initial Value
H'FFC2
Wait-state control register
WSCR
R/W
H'08
5.2
Register Description
5.2.1
Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller
(WSC) and specifies the number of wait states. It also controls RAM area setting for dual-power-
supply flash memory, selection/non-selection of single-power-supply flash memory control
registers, and frequency division of the clock signals supplied to the supporting modules.
Bit
7
6
5
4
3
2
WMS0
0
1
0
RAMS*1 RAM0*1 CKDBL FLSHE*2 WMS1
WC1
0
WC0
0
Initial value
Read/Write
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Notes: *1 These bits are valid only in the H8/3437F and H8/3434F (dual-power-supply on-chip
flash memory versions).
*2 This bit is valid only in the H8/3437SF (S-mask model, single-power-supply on-chip
flash memory version).
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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HITACHI [ HITACHI SEMICONDUCTOR ]
