HSP3824
CONFIGURATION REGISTER 9 ADDRESS (24h) I/O DEFINITION REGISTER
Bit 5
Bit 4
Bit 3
This control bit selects the active level of the Clear Channel Assessment (CCA) output pin 32.
Logic 1 = CCA active 1.
Logic 0 = CCA active 0.
This control bit selects the active level of the Energy Detect (ED) output which is an output pin at the test port, pin 45.
Logic 1 = ED active 0.
Logic 0 = ED active 1.
This control bit selects the active level of the Carrier Sense (CRS) output pin which is an output pin at the test port, pin
46.
Logic 1 = CRS active 0.
Logic 0 = CRS active 1.
Bit 2
Bit 1
Bit 0
This control bit selects the active level of the transmit ready (TX_RDY) output pin 5.
Logic 1 = TX_RDY active 0.
Logic 0 = TX_RDY active 1.
This control bit selects the active level of the transmit enable (TX_PE) input pin 2.
Logic 1 = TX_PE active 0.
Logic 0 = TX_PE active 1.
This control bit selects the phase of the transmit output clock (TXCLK) pin 4.
Logic 1 = Inverted TXCLK.
Logic 0 = NON-Inverted TXCLK
CONFIGURATION REGISTER 10 ADDRESS (28h) RSSI VALUE REGISTER
Bits 0 - 7
This is a read only register reporting the value of the RSSI analog input signal from the on chip 6-bit ADC. This register
is updated at (chip rate/11). Bits 7 and 6 are not used and set to Logic 0.
Example:
BITS (0:7)
RANGE
RSSI_STAT
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
0 0 1 1 1 1 1 1
00h (Min)
3Fh (Max)
CONFIGURATION REGISTER 11 ADDRESS (2ch) A/D CAL POS REGISTER
Bits 0 - 7
Bits 0 - 7
Bits 0 - 7
This 8-bit control register contains a binary value used for positive increment for the level adjusting circuit of the A/D
reference. The larger the step the faster the level reaches saturation.
CONFIGURATION REGISTER 12 ADDRESS (30h) A/D CAL NEG REGISTER
This 8-bit control register contains a binary value used for the negative increment for the level adjusting reference of
the A/D. The number is programmed as 256 - the value wanted since it is a negative number.
CONFIGURATION REGISTER 13 ADDRESS (34h) TX SPREAD SEQUENCE (HIGH)
This 8-bit register is programmed with the upper byte of the transmit spreading code. This code is used for both the I
and Q signalling paths of the transmitter. This register combined with the lower byte TX_SPREAD(LOW) generates a
transmit spreading code programmable up to 16 bits. Code lengths permitted are 11, 13, 15, and 16. Right justified
MSB first.
31
HARRIS [ HARRIS CORPORATION ]
