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HSP3824VI 参数 Datasheet PDF下载

HSP3824VI图片预览
型号: HSP3824VI
PDF下载: 下载PDF文件 查看货源
内容描述: 直接序列扩频基带处理器 [Direct Sequence Spread Spectrum Baseband Processor]
分类和应用: 电信集成电路
文件页数/大小: 41 页 / 278 K
品牌: HARRIS [ HARRIS CORPORATION ]
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HSP3824  
CONFIGURATION REGISTER 2 ADDRESS (08h) MODEM CONFIGURATION REGISTER C  
Bit 7, 6  
These control bits are used to select the number of chips per symbol used in the I and Q paths of the receiver matched  
filter correlators (see table below).  
CHIPS PER SYMBOL  
BIT 7  
BIT 6  
11  
13  
15  
16  
0
0
1
1
0
1
0
1
Bit 5  
This control bit is used to disable the CRC16 check. When this bit is set, the processor will accept the received packet  
and any packet error checks have to be detected externally. The HSP3824 will remain in the receive mode until either  
the carrier is lost or the network processor resets the device to the acquisition mode, or if, in modes 2 or 3, the length  
times out.  
Logic 1 = Disable receiver error checks.  
Logic 0 = Enable receiver checks.  
Bit 4, 3  
These control bits are used to select the divide ratio for the demodulators receive chip clock timing.The value of N is  
determined by the following equation:  
Symbol Rate = MCLK/(N x Chips per symbol).  
MASTER CLOCK/N  
BIT 4  
BIT 3  
N = 2  
N = 4  
N = 8  
N = 16  
0
0
1
1
0
1
0
1
Bit 2  
This control bit sets the receiver into single or dual antenna mode. The Preamble acquisition processing length and  
whether the modem scans antennas is controlled by this bit. If in single antenna mode, the ANT_SEL pin reflects CR0  
bit 6 otherwise it reflects the receiver’s choice of antenna.  
Logic 0 = Acquisition processing is for dual antenna acquisition.  
Logic 1 = Acquisition processing is for single antenna acquisition.  
Bit 1, 0  
These control bits are used to indicate one of the four Preamble Header modes for receiving data. Each of the modes  
includes different combinations of Header fields. Users can choose the mode with the fields that are more appropriate  
for their networking requirements. The Header fields that are combined to form the various modes are:  
• SFD field  
• CRC16 field  
• Data length field (indicates the number of data bits that follow the Header information)  
• Full protocol Header  
INPUT MODE  
BIT 1  
BIT 0  
RECEIVE PREAMBLE - HEADER FIELDS  
Preamble, with SFD Field  
0
1
2
3
0
0
1
1
0
1
0
1
Preamble, with SFD, CRC16  
Preamble, with SFD Length, CRC16  
Preamble, with Full Protocol Header  
CONFIGURATION REGISTER 3 ADDRESS (0Ch) MODEM CONFIGURATION REGISTER D  
Bit 7  
Reserved (must set to “0”).  
28  
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