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HSP3824 参数 Datasheet PDF下载

HSP3824图片预览
型号: HSP3824
PDF下载: 下载PDF文件 查看货源
内容描述: 直接序列扩频基带处理器 [Direct Sequence Spread Spectrum Baseband Processor]
分类和应用:
文件页数/大小: 41 页 / 278 K
品牌: HARRIS [ HARRIS CORPORATION ]
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HSP3824  
CONFIGURATION REGISTER 19 ADDRESS (4Ch) RSSI THRESHOLD, ENERGY DETECT  
Bits 0 - 7  
This register contains the value for the RSSI threshold for measuring and generating energy detect (ED). When the  
RSSI exceeds the threshold ED is declared. ED indicates the presence of energy in the channel. The threshold that  
activates ED is programmable. Bits 7 an 6 of this register are not used and set to Logic 0.  
MSB  
LSB  
Bits (0:7)  
7 6 5 4 3 2 1 0  
0 0 0 0 0 0 0 0  
0 0 1 1 1 1 1 1  
00h (Min)  
3Fh (Max)  
RSSI_STAT  
CONFIGURATION REGISTER 20 ADDRESS (50h) RX SPREAD SEQUENCE (HIGH)  
Bits 0 - 7  
Bits 0 - 7  
Bits 0 - 7  
This 8-bit register is programmed with the upper byte of the receive despreading code. This code is used for both the  
I and Q signalling paths of the receiver. This register combined with the lower byte RX_SPRED(LOW) generates a  
receive despreading code programmable up to 16 bits. Right justified MSB first. See address 13 and 14 for example.  
CONFIGURATION REGISTER 21 ADDRESS (54h) RX SPREAD SEQUENCE (LOW)  
This 8-bit register is programmed with the lower byte of the receiver despreading code. This code is used for both the  
I and Q signalling paths of the receiver. This register combined with the upper byte RX_SPRED(HIGH) generates a  
receive despreading code programmable up to 16 bits.  
CONFIGURATION REGISTER 22 ADDRESS (58h) RX SIGNAL QUALITY 1 ACQ (HIGH) THRESHOLD  
This control register contains the upper byte bits (8 - 14) of the bit sync amplitude signal quality threshold used for  
acquisition. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude  
signal quality measurements made during acquisition at each antenna dwell. This threshold comparison is added with  
the SQ2 threshold in registers 30 and 31 for acquisition. A lower value on this threshold will increase the probability of  
detection and the probability of false alarm. Set the threshold according to instructions in the text.  
CONFIGURATION REGISTER 23 ADDRESS (5Ch) RX SIGNAL QUALITY 1 ACQ THRESHOLD (LOW)  
Bits 0 - 7  
Bits 0 - 7  
Bits 0 - 7  
Bits 0 - 7  
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for ac-  
quisition. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude sig-  
nal quality measurement made during acquisition at each antenna dwell.  
CONFIGURATION REGISTER 24 ADDRESS (60h) RX SIGNAL QUALITY 1 ACQ READ (HIGH)  
This status register contains the upper byte bits (8 - 14) of the measured signal quality threshold for the bit sync am-  
plitude used for acquisition. This register combined with the lower byte represents a 15-bit value, representing the mea-  
sured bit sync amplitude. This measurement is made at each antenna dwell and is the result of the best antenna.  
CONFIGURATION REGISTER 25 ADDRESS (64h) RX SIGNAL QUALITY 1 ACQ READ (LOW)  
This register contains the lower byte bits (0 - 7) of the measured signal quality threshold for the bit sync amplitude used  
for acquisition. This register combined with the higher byte represents a 15-bit value, of the measured bit sync ampli-  
tude. This measurement is made at each antenna dwell and is the result of the best antenna.  
CONFIGURATION REGISTER 26 ADDRESS (68h) RX SIGNAL QUALITY 1 DATA THRESHOLD (HIGH)  
This control register contains the upper byte bits (8-14) of the bit sync amplitude signal quality threshold used for drop  
lock decisions. This register combined with the lower byte represents a 15-bit threshold value for the bit sync amplitude  
signal quality measurements, made every 128 symbols. These thresholds set the drop lock probability. A higher value  
will increase the probability of dropping lock.  
CONFIGURATION REGISTER ADDRESS 27 (6Ch) RX SIGNAL QUALITY 1 DATA THRESHOLD (LOW)  
Bits 0 - 7  
This control register contains the lower byte bits (0 - 7) of the bit sync amplitude signal quality threshold used for drop  
lock decisions. This register combined with the upper byte represents a 15-bit threshold value for the bit sync amplitude  
signal quality measurements, made every 128 symbols.  
33  
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