HSP3824
CONFIGURATION REGISTER 7 ADDRESS (1Ch) MODEM STATUS REGISTER A (Continued)
Bit 5
Bit 4
Bit 3
This status bit indicates the present state of clear channel assessment (CCA) which is output pin 32. The CCA is being
asserted as a result of a channel energy monitoring algorithm that is a function of RSSI, carrier sense, and time out
counters that monitor the channel activity.
This status bit, when active indicates Carrier Sense, or PN lock.
Logic 1: Carrier present.
Logic 0: No Carrier Sense.
This status bit indicates whether the RSSI signal is above or below the programmed RSSI 6-bit threshold setting. This
signal is referred as Energy Detect (ED).
Logic 1: RSSI is above the programmed threshold setting.
Logic 0: RSSI is below the programmed threshold setting.
Bit 2
Bit 1
Bit 0
This bit indicates the status of the output control pin MD_RDY (pin 34). It signals that a valid Preamble/Header has
been received and that the next available bit on the TXD bus will be the first data packet bit.
Logic 1: Envelopes the data packet as it becomes available on pin 3 (TXD).
Logic 0: No data packet on TXD serial bus.
This status bit indicates whether the external device has acknowledged that the channel is clear for transmission. This
is the same as the input signal TX_PE on pin 2.
Logic 1 = Acknowledgment that channel is clear to transmit.
Logic 0 = Channel is NOT clear to transmit.
This status bit indicates that a valid CRC16 has been calculated. The CRC16 is calculated on the Header information.
The CRC16 does not cover the preamble bits.
Logic 1 = Valid CRC16 check.
Logic 0 = Invalid CRC16 check.
CONFIGURATION REGISTER 8 ADDRESS (20h) MODEM STATUS REGISTER B
Bit 7
Bit 6
This status bit is meaningful only when the device operates under the full protocol mode. Errors imply CRC errors of
the header fields.
Logic 0 = Valid packet received.
Logic 1 = Errors in received packet.
This bit is used to indicate the status of the SFD search timer. The device monitors the incoming Header for the SFD.
If the timer, times out the HSP3824 returns to its signal acquisition mode looking to detect the next Preamble and
Header.
Logic 1 = SFD not found, return to signal acquisition mode.
Logic 0 = No time out during SFD search.
Bit 5
This status bit is used to indicate the modulation type for the data packet. This signal is generated by the header de-
tection circuitry in the receive interface.
Logic 0 = DBPSK.
Logic 1 = DQPSK.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused, don’t care.
Unused, don’t care.
Unused, don’t care.
Unused, don’t care.
Unused, don’t care.
CONFIGURATION REGISTER 9 ADDRESS (24h) I/O DEFINITION REGISTER
This register is used to define the phase of clocks and other interface signals.
Bit 7
Bit 6
This bit needs to always be set to logic 0.
This control bit selects the active level of the MD_RDY output pin 34.
Logic 1 = MD_RDY is active 0.
Logic 0 = MD_RDY is active 1.
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