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HSP3824 参数 Datasheet PDF下载

HSP3824图片预览
型号: HSP3824
PDF下载: 下载PDF文件 查看货源
内容描述: 直接序列扩频基带处理器 [Direct Sequence Spread Spectrum Baseband Processor]
分类和应用:
文件页数/大小: 41 页 / 278 K
品牌: HARRIS [ HARRIS CORPORATION ]
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HSP3824  
These two thresholds, bit sync amplitude CR (22 and 23)  
Data Demodulation and Tracking  
Description  
and phase error CR (30 and 31) are used to determine if the  
desired signal is present. If the thresholds are set too “low”,  
there is the probability of missing a high signal to noise  
detection due to processing a false alarm. If they are set too  
“high”, there is the probability of missing a low signal to noise  
detection. For the bit sync amplitude, “high” actually means  
high amplitude while for phase noise “high” means high SNR  
or low noise.  
The signal is demodulated from the correlation peaks  
tracked by the symbol timing loop (bit sync). The frequency  
and phase of the signal is corrected from the NCO that is  
driven by the phase locked loop. Demodulation of the DPSK  
data in the early stages of acquisition is done by delay and  
subtraction of the phase samples. Once phase locked loop  
tracking of the carrier is established, coherent demodulation  
is enabled for better performance. Averaging the phase  
errors over 16 symbols gives the necessary frequency infor-  
mation for proper NCO operation. The signal quality is taken  
as the variance in this estimate.  
A recommended procedure is to set these thresholds individu-  
ally optimizing each one of them to the same false alarm rate  
with no desired signal present. Only the background environ-  
ment should be present, usually additive gaussian white noise  
(AGWN). When programming each threshold, the other  
threshold is set so that it always indicates that the signal is  
present. Set register CR22 to 00h while trying to determine  
the value of the phase error signal quality threshold for regis-  
ters CR 30 and 31. Set register CR30 to FFh while trying to  
determine the value of the Bit sync. amplitude signal quality  
threshold for registers 22 and 23. Monitor the Carrier Sense  
(CRS) output (TEST 7, pin 46) and adjust the threshold to pro-  
duce the desired rate of false detections. CRS indicates valid  
initial PN acquisition. After both thresholds are programmed in  
the device the CRS rate is a logic “and” of both signal qualities  
rate of occurrence over their respective thresholds and will  
therefore be much lower than either.  
There are two signal quality measurements that are per-  
formed in real time by the device and they set the demodula-  
tor performance. The thresholds for these signal quality  
measurements are user programmable. The same two sig-  
nal quality measures, phase error and bit sync. amplitude,  
that are used in acquisition are also used for the data drop  
lock decision. The data thresholds, though, are programmed  
independently from the acquisition thresholds. If the radio  
uses the network processor to determine when to drop the  
signal, the thresholds for these decisions should be set to  
their limits allowing data demodulation even with poor signal  
reception. Under this configuration the HSP3824 data moni-  
tor mechanism is essentially bypassed and data monitoring  
becomes the responsibility of the network processor.  
PN Correlator Description  
These signal quality measurements are integrated over 128  
symbols as opposed to 16 symbol intervals for acquisition, so  
the minimum time to drop lock based with these thresholds is  
128 symbols or 128ms at 1 MSPS. Note that other than the  
data thresholds, non-detection of the SFD can cause the  
HSP3824 to drop lock and return its acquisition mode.  
The PN correlator is designed to handle BPSK spreading  
with carrier offsets up to ±50ppm and 11,13,15 or 16 chips  
per symbol. Since the spreading is BPSK, the correlator is  
implemented with two real correlators, one for the I and one  
for the Q channel.The same sequence is always used for  
both I an Q correlators. The TX sequence can be pro-  
grammed as a different sequence from the RX sequence.  
This allows a full duplex link with different spreading parame-  
ters for each direction.  
Configuration Register 41 sets the search timer for the SFD.  
This register sets this time-out length in symbols for the  
receiver. If the time out is reached, and no SFD is found, the  
receiver resets to the acquisition mode. The suggested value  
is preamble symbols + 16 symbols. If several transmit pream-  
ble lengths are used by various transmitters in a network, the  
longest value should be used for the receiver settings.  
The correlators are time invariant matched filters otherwise  
known as parallel correlators. They use two samples per  
chip. The correlator despreads the samples from the chip  
rate back to the original data rate giving 10.4dB processing  
gain for 11 chips per bit. While despreading the desired sig-  
nal, the correlator spreads the energy of any non correlating  
interfering signal.  
Procedure to Set Signal Quality Registers  
CR 26, 27, 34, AND 35 (RX_SQX_IN_DATA) are pro-  
grammed to hold the threshold values that are used to drop  
lock if the signal quality drops below their values. These can  
be set to their limit values if the external network processor  
is used for drop lock decisions instead of the HSP3824  
demodulator. The signal quality values are averaged over  
128 symbols and if the bit sync amplitude value drops below  
its threshold or the phase noise rises over its threshold, the  
link is dropped and the receiver returnes to the acquisition  
mode. These values should typically be different for BPSK  
and QPSK since the operating point in SNR differs by 3dB. If  
the receiver is intended to receive both BPSK and QPSK  
modulations, a compromise value must be used or the net-  
work processor can control them as appropriate.  
Based on the fact that correlator output pulse is used for bit  
timing, the HSP3824 can not be used for any non spread  
applications.  
In programming the correlator functions, there are two sets  
of configuration registers that are used to program the  
spread sequences of the transmitter and the receiver. They  
are CR 13 and 14 for transmitter and CR 20 and 21 for the  
receiver. In addition, CR2 and CR3 define the sequence  
length or chips per symbol for the receiver and transmitter  
respectively. These are carried in bits 6 and 7 of CR2 and  
bits 5 and 6 of CR3. More programming details are given in  
the Control Registers section of this document.  
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