HSP3824
Finally, CR 17 and CR 18 are used to set the time out the resulting signals. These operations are illustrated in Fig-
parameters before the CCA algorithm declares permission ure 14 which is an overall block diagram of the receiver pro-
for transmission.
cessor. Input samples from the I and Q ADC converters are
correlated to remove the spreading sequence. The magni-
tude of the correlation pulse is used to determine the symbol
timing. The sample stream is decimated to the symbol rate
and the phase is corrected for frequency offset prior to PSK
demodulation. Phase errors from the demodulator are fed to
the NCO through a lead/lag filter to achieve phase lock. The
variance of the phase errors is used to determine signal
quality for acquisition and lock detection.
Receiver Description
The receiver portion of the baseband processor, performs
ADC conversion and demodulation of the spread spectrum
signal. It correlates the PN spread symbols, then demodu-
lates the DBPSK or DQPSK symbols. The demodulator
includes a frequency loop that tracks and removes the car-
rier frequency offset. In addition it tracks the symbol timing,
and differentially decodes and descrambles the data. The
data is output through the RX Port to the external processor.
Acquisition Description
The PRISM baseband processor uses either a dual antenna
mode of operation for compensation against multipath inter-
ference losses or a single antenna mode of operation with
faster acquisition times.
A common practice for burst mode communications systems
is to differentially modulate the signal, so that a DPSK
demodulator can be used for data recovery. This form of
demodulator uses each symbol as a phase reference for the
next one. It offers rapid acquisition and tolerance to rapid Two Antenna Acquisition
phase fluctuations at the expense of lower bit error rate
(BER) performance.
During the 2 antenna (diversity) mode the two antennas are
scanned in order to find the one with the best representation
The PRISM baseband processor, HSP3824 uses differential of the signal. This scanning is stopped once a suitable signal
demodulation for the initial acquisition portion of the pro- is found and the best antenna is selected.
cessing and then switches to coherent demodulation for the
A projected worst case time line for the acquisition of a signal
rest of the acquisition and data demodulation. The HSP3824
in the two antenna case is shown in Figure 15. The synchroni-
is designed to achieve rapid settling of the carrier tracking
zation part of the preamble is 128 symbols long followed by a
loop during acquisition. Coherent processing substantially
16-bit SFD. The receiver must scan the two antennas to deter-
improves the BER performance margin. Rapid phase fluctu-
mine if a signal is present on either one and, if so, which has
ations are handled with a relatively wide loop bandwidth.
the better signal. The timeline is broken into 16 symbol blocks
The baseband processor uses time invariant correlation to (dwells) for the scanning process. This length of time is neces-
strip the PN spreading and polar processing to demodulate sary to allow enough integration of the signal to make a good
TX
POWER
RAMP
SFD
126 SYMBOL SYNC
16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 7S 7S
16 SYMBOLS
A1
2
A1
A2
A1
A2
A1
A2
A1
A1 A1
JUST
MISSED
DET
NO
SIG
FOUND
ANT2
DETECT
ANT1
VERIFY
ANT1
CHECK
ANT2
CHECK
ANT2
SYMB
TIMING
DETECT
ANT1
SFD DET
START DATA
SEED
ANT1
DESCRAMBLER
INTERNAL
SET UP TIME
NOTES:
1. Worst Case Timing; antenna dwell starts before signal is full strength.
2. Time line shown assumes that antenna 2 gets insufficient signal.
FIGURE 15. DUAL ANTENNA ACQUISITION TIMELINE
TX
POWER
RAMP
SFD
78 SYMBOL SYNC
16 SYMBOLS
16 SYMBOLS
16 SYMBOLS
16 SYMBOLS
7 SYM
7 SYM
16 SYMBOLS
2
JUST
MISSED
DET
SYMB
TIMING
DETECT
SFD DET
START DATA
VERIFY
SEED
DESCRAMBLER
INTERNAL
SET UP TIME
FIGURE 16. SINGLE ANTENNA ACQUISITION TIMELINE
20
HARRIS [ HARRIS CORPORATION ]
