HSP3824
acquisition decision. This worst case time line example uses a 78 symbol sequence with 2 more for power ramping
assumes that the signal is present on antenna A1 only (A2 is of the RF front of the radio. This scheme deletes the second
blocked). It further assumes that the signal arrives part way antenna dwells but performs the same otherwise. It verifies
into the first A1 dwell such as to just barely miss detection. the signal after initial detection for lower false alarm proba-
The signal and the scanning process are asynchronous and bility.
the signal could start anywhere. In this timeline, it is assumed
that all 16 symbols are present, but they were missed due to
Acquisition Signal Quality Parameters
power amplifier ramp up. Since A2 has insufficient signal, the
first A2 dwell after the start of the preamble also fails detec-
tion. The second A1 dwell after signal start is successful and a
symbol timing measurement is achieved.
Two measures of signal quality are used to determine acqui-
sition and drop lock decisions. The first method of determin-
ing signal presence is to measure the correlator output (or
bit sync) amplitude. This measure, however, flattens out in
the range of high BER and is sensitive to signal amplitude.
The second measure is phase noise and in most BER sce-
narios it is a better indication of good signals plus it is insen-
sitive to signal amplitude. The bit sync amplitude and phase
noise are integrated over each block of 16 symbols used in
acquisition or over blocks of 128 symbols in the data demod-
ulation mode. The bit sync amplitude measurement repre-
sents the peak of the correlation out of the PN correlator.
Figure 17 shows the correlation process. The signal is sam-
Meanwhile signal quality and signal frequency measure-
ments are made simultaneous with symbol timing measure-
ments. When the bit sync level, SQ1, and Phase variance
SQ2 are above their user programmable thresholds, the sig-
nal is declared present for the antenna with the best signal.
More details on the Signal Quality estimates and their pro-
grammability are given in the Acquisition Signal Quality
Parameters section of this document.
At the end of each dwell, a decision is made based on the rel- pled at twice the chip rate (i.e. 22 MSPS). The one sample
ative values of the signal qualities of the signals on the two that falls closest to the peak is used for a bit sync amplitude
antennas. In the example, antenna A1 is the one selected, so sample for each symbol. This sample is called the on-time
the recorded symbol timing and carrier frequency for A1 are sample. High bit sync amplitude means a good signal. The
used thereafter for the symbol timing and the PLL of the NCO early and late samples are the two adjacent samples and
to begin carrier de-rotation and demodulation.
are used for tracking.
Prior to initial acquisition the NCO was inactive and DPSK The other signal quality measurement is based on phase
demodulation processing was used. Carrier phase measure- noise and that is taken by sampling the correlator output at the
ment are done on a symbol by symbol basis afterward and correlator peaks. The phase changes due to scrambling are
coherent DPSK demodulation is in effect. After a brief setup removed by differential demodulation during initial acquisition.
time as illustrated on the timeline of Figure 15, the signal Then the phase, the phase rate and the phase variance are
begins to emerge from the demodulator.
measured and integrated for 16 symbols. The phase variance
is used for the phase noise signal quality measure. Low phase
noise means a stronger received signal.
If the descrambler is used it takes 7 more symbols to seed
the descrambler before valid data is available. This occurs in
time for the SFD to be received. At this time the demodulator Procedure to Set Acq. Signal Quality
is tracking and in the coherent PSK demodulation mode it Parameters (Example)
will no longer scan antennas.
There are four registers that set the acquisition signal quality
One Antenna Acquisition
thresholds, they are: CR 22, 23, 30, and 31
(RX_SQX_IN_ACQ). Each threshold consists of two bytes,
high and low that hold a 16-bit number.
When only one antenna is being used, the user can delete
the antenna switch and shorten the acquisition sequence.
Figure 16 shows the single antenna acquisition timeline. It
SAMPLES
AT 2X CHIP
RATE
CORRELATION
PEAK
CORRELATION TIME
T0
T0 + 1µs
CORRELATOR
OUTPUT
T0 + 2µs
CORRELATOR OUTPUT IS
THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE
RECEIVED SIGNAL
EARLY
ON-TIME
LATE
REPEATS
FIGURE 17. CORRELATION PROCESS
21
HARRIS [ HARRIS CORPORATION ]
