CD22354A, CD22357A
Functional Description
CLOCKING OPTIONS
MASTER CLOCK
Power Supply Sequencing
FREQUENCY SELECTED
BCLK /CLKSEL
Do not apply input signal or load on output before powering
up VCC supply. Care must be taken to ensure that DX pin
goes on common back plane (with other DX pins from other
chips). DX pin cannot drive >50mA before Power-Up. This
will cause the part to latch up.
R
MODE
(PIN 7)
CD22354A (µ) CD22357A (A)
Asynchronous
or
Synchronous
Clocked
1.536MHz or
1.544MHz
2.048MHz
Synchronous
0
2.048MHz
1.536MHz or
1.544MHz
Power-Up
When power is first applied, the Power-On reset circuitry ini-
tializes the CODEC and places it in a Power-Down mode.
When the CODEC returns to an active state from the Power-
Synchronous 1(or open circuit) 1.536MHz or
1.544MHz
2.048MHz
Down mode, the receive output is muted briefly to minimize Asynchronous Operation
turn-on “click”.
(Transmit and Receive Sections use Separate Master
Clocks)
To power up the device, there are two methods available.
For the CD22357A, the MCLKX and MCLKR must be
2.048MHz and for the CD22354A must be 1.536MHz or
1.544MHz. These clocks need not be synchronous. However,
for best transmission performance, it is recommended that
MCLKX and MCLKR be synchronous.
1. A logical zero at MCLKR/PDN will power up the device,
provided FSX or FSR pulses are present.
2. Alternatively, a clock (MCLKR) must be applied to MCLKR/
PDN and FSX or FSR pulses must be present.
Power-Down
For 1.544MHz operation the device automatically compensates
for the 193rd clock pulse each frame. FSX starts the encoding
operation and must be synchronous with MCLKX and BCLKX.
FSR starts the decoding operation and must be synchronous
with BCLKR. BCLKR must be clocked in asynchronous opera-
tion. BCLKX and BCLKR may be between 64kHz - 2.04MHz.
Two power-down modes are available.
1. A logical 1 at MCLKR/PDN, after approximately 0.5ms, will
power down the device.
2. Alternatively, hold both FSX and FSR continuously low,
the device will power down approximately 0.5ms after the
last FSX or FSR pulse.
Short-Frame Sync Mode
When the power is first applied, the power initialization circuitry
places the CODEC in a short-frame sync mode. In this mode
both frame sync pulses must be 1 bit-clock period long, with the
timing relationship shown in Figure 1.
Synchronous Operation
(Transmit and Receive Sections use the Same Master
Clock)
The same master clock and bit-clock should be used for the
receive and transmit sections. MCLKX (pin 9) is used to pro-
vide the master clock for the transmit section; the receive
section will use the same master clock if the MCLKR/PDN
(pin 8) is grounded (synchronous operation), or at V+
(power-down mode). MCLKR/PDN may be clocked only if a
clock is provided at BCLKR/CLKSEL (pin 7) as in asynchro-
nous operation.
With FSX high during the falling edge of the BCLKX, the next
rising edge of BCLKX enables the DX tristate output buffer,
which will output the sign bit. The following rising seven edges
clock out the remaining seven bits upon which the next falling
edge will disable the DX output.
With FSR high during the falling edge of the BCLKR (BCLKX in
synchronous mode), the next falling edge of BCLKR latches in
the sign bit. The following seven edges latch in the seven
remaining bits.
The BCLKX (pin 10) is used to provide the bit clock to the
transmit section. In synchronous operation, this bit clock is
also used for the receive section if MCLKR/PDN (pin 8) is
grounded. BCLKR/CLKSEL (pin 7) is then used to select the
Long-Frame Sync Mode
proper internal frequency division for 1.544MHz, 1.536MHz In this mode of operation, both of the frame sync pulses must
or 2.048MHz operation (see Table below). For 1.544MHz be three or more bit-clock periods long with the timing relation-
operation, the device automatically compensates for the ship shown in Figure 2.
193rd clock pulse each frame.
Based on the transmit frame sync FSX, the CODEC will sense
Each FSX pulse begins the encoding cycle and the PCM whether short or long-frame sync pulses are being used.
data from the previous encode cycle is shifted out of the
For 64kHz operation the frame sync pulse must be kept low for
enabled DX output on the leading edge of BCLKX. After 8 bit-
a minimum of 160ns.
clock periods, the tristate DX output is returned to a high
impedance state. With an FSR pulse, PCM data is latched
via the DR input on the negative edge of the BCLKX. FSX
and FSR must be synchronous with MCLKX.
The DX tristate output buffer is enabled with the rising edge of FSX
or the rising edge of the BCLKX, whichever comes later and the
first bit clocked out is the sign bit. The following seven rising edges
of the BCLKX clock out the remaining seven bits. The DX output is
disabled by the next falling edge of the BCLKX following the 8th
rising edge or by FSX going low whichever comes later.
4-172
HARRIS [ HARRIS CORPORATION ]
