CD22354A, CD22357A
Electrical Specifications (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Hold Time from 3rd Period of Bit
Clock Low to Frame Sync
t
Long Frame Sync Pulse
(from 3 to 8-Bit Clock Periods Long)
100
-
-
ns
HBFI
(FS or FS )
X
R
Minimum Width of the Frame
Sync Pulse (Low Level)
t
64K Bit/s Operating Mode
160
-
-
ns
WFL
NOTE:
1. For short frame sync timing, FS and FS must go high while their respective bit clocks are high.
X
R
Pin Descriptions
PIN NO.
SYMBOL
V-
DESCRIPTION
1
2
3
4
5
Negative power supply, V- = -5V ±5%.
GND
Analog and digital ground. All signals referenced to this pin.
Analog output of RECEIVE FILTER.
VF O
R
V+
Positive power supply, V+ = 5V ±5%.
FS
Receive Frame Sync Pulse which enables BCLK to shift PCM data into D . FS is an 8kHz PULSE
R R R
R
TRAIN.
6
7
D
R
Receive Data Input. PCM data is shifted into D following the FS leading edge.
R
R
BCLK /CLK-
The Receive Bit Clock, which shifts data into D after the frame sync leading edge, may vary from 64kHz
R
R
SEL
to 2.048MHz. Alternatively, the leading edge may be a logic input which selects either 1.536MHz/
1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLK is used for both transmit and
X
receive directions.
8
MCLK /PDN
Receive Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLK ,
R
X
but best performance is realized from synchronous operation. When this pin is continuously connected
low, MCLK is selected for all internal timing. When this pin is continuously connected high, the device is
X
powered down.
9
MCLK
Transmit Master Clock. Must be 1.536MHz, 1.544MHz or 2.048MHz. May be asynchronous with MCLK ,
X
R
but best performance is realized from synchronous operation.
10
BCLK
The Bit Clock which shifts out the PCM Data on D . May vary from 64kHz to 2.048MHz, but must be syn-
X
X
chronous with MCLK
X.
11
12
D
The THREE-STATE PCM Data Output which is enabled by FS .
X
X
FS
TS
Transmit Frame Sync Pulse input which enables BCLK to shift out the data on D . FS is an 8kHz
X X X
PULSE TRAIN.
X
13
14
15
16
Open drain output which pulses low during the encoder time slot.
Transmit gain adjust.
X
GS
X
VF I-
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifier.
X
VF I+
X
4-171
HARRIS [ HARRIS CORPORATION ]
