CD22354A, CD22357A
Electrical Specifications
PARAMETER
AC TIMING
Frequency of Master Clocks
1/t
PM
Depends on the Device Used
and the BCLK
R
/CLKSEL Pin
MCLK
X
and MCLK
R
Width of Master Clock High
Width of Master Clock Low
Rise Time of Master Clock
Fall Time of Master Clock
Set-up Time from BCLK
X
High
(and FS
X
in Long Frame Sync
Mode) to MCLK
X
Falling Edge
Period of Bit Clock
Width of Bit Clock High
Width of Bit Clock Low
Rise Time of Bit Clock
Fall Time of Bit Clock
Hold Time from Bit Clock Low to
Frame Sync
Hold Time from Bit Clock High to
Frame Sync
Set-up Time from Frame Sync to
Bit Clock Low
Delay Time from BCLK
X
High to
Data Valid
Delay Time to TS
X
Low
Delay Time from BCLK
X
Low or
FS
X
Low to Data Output Disabled
Delay Time to Valid Data from
FS
X
or BCLK
X
, Whichever Comes
Later
Set-up Time from D
R
Valid to
BCLK
R/X
Low
Hold Time from BCLK
R/X
Low to
D
R
Invalid
Set-up Time from FS
X/R
to
BCLK
X/R
Low
Hold Time from BCLK
X/R
Low to
FS
X/R
Low
t
WMH
t
WML
t
RM
t
FM
t
SBFM
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
MCLK
X
and MCLK
R
First Bit Clock after the Leading
Edge of FS
X
-
-
-
160
160
-
-
100
1.536
1.544
2.048
-
-
-
-
-
-
-
-
-
-
50
50
-
MHz
MHz
MHz
ns
ns
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
t
PB
t
WBH
t
WBL
t
RB
t
FB
t
HBF
t
HOLD
t
SFB
t
DBD
t
XDP
t
DZC
t
DZF
C
L
= 0pF to 150pF
V
IH
= 2.2V
V
IL
= 0.6V
t
PB
= 488ns
t
PB
= 488ns
Long Frame Only
485
160
160
-
-
0
488
-
-
-
-
-
15,725
-
-
50
50
-
ns
ns
ns
ns
ns
ns
Short Frame Only
0
-
-
ns
Long Frame Only
80
-
-
ns
Load = 150pF plus 2 LSTTL
Loads
Load = 150pF plus 2 LSTTL
Loads
0
-
180
ns
-
-
140
ns
50
-
165
ns
20
-
165
ns
t
SDB
t
HBD
t
SF
Short Frame Sync Pulse
(1 or 2 Bit Clock Periods Long)
(Note 1)
Short Frame Sync Pulse
(1 or 2 Bit Clock Periods Long)
(Note 1)
50
-
-
ns
50
-
-
ns
50
-
-
ns
t
HF
100
-
-
ns
4-170
HARRIS [ HARRIS CORPORATION ]
